Hi Bill,
Some little things about the patch...
On Thu, Jun 23, 2016 at 04:44:27PM -0500, Bill Schmidt wrote:
> We no longer have a half-clever implementation to construct an infinity
> inside vector registers, or the full-clever one that Segher proposed in
> response. :) We can try to add that support later if desired.
For posterity:
Use vspltisw A,N ; vsrw B,A,A ; vslo D,B,A to create in D:
N=-16 ffff_0000_0000_0000_0000_0000_0000_0000 (ieee128 -Inf)
N=-17 7fff_0000_0000_0000_0000_0000_0000_0000 (ieee128 +Inf)
> @@ -35569,6 +35639,7 @@ static struct rs6000_opt_mask const rs6000_builtin
> { "hard-dfp", RS6000_BTM_DFP, false, false },
> { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
> { "long-double-128", RS6000_BTM_LDBL128, false, false },
> + { "float128", RS6000_BTM_FLOAT128, false, false },
The previous entries use tabs for indentation.
> --- gcc/config/rs6000/rs6000.h (revision 237619)
> +++ gcc/config/rs6000/rs6000.h (working copy)
> @@ -2689,6 +2689,7 @@ extern int frame_pointer_needed;
> #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating
> point. */
> #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
> #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
> +#define RS6000_BTM_FLOAT128 MASK_P9_VECTOR /* IEEE 128-bit float. */
Here, too.
> @@ -2705,7 +2706,8 @@ extern int frame_pointer_needed;
> | RS6000_BTM_CELL \
> | RS6000_BTM_DFP \
> | RS6000_BTM_HARD_FLOAT \
> - | RS6000_BTM_LDBL128)
> + | RS6000_BTM_LDBL128 \
> + | RS6000_BTM_FLOAT128)
And here. And more later. Let's try to stick to one style, at least
locally.
> --- gcc/config/rs6000/rs6000.md (revision 237619)
> +++ gcc/config/rs6000/rs6000.md (working copy)
> @@ -13326,7 +13326,25 @@
> "xssqrtqp %0,%1"
> [(set_attr "type" "vecdiv")])
>
> -(define_insn "copysign<mode>3"
> +(define_expand "copysign<mode>3"
> + [(use (match_operand:IEEE128 0 "altivec_register_operand" ""))
> + (use (match_operand:IEEE128 1 "altivec_register_operand" ""))
> + (use (match_operand:IEEE128 2 "altivec_register_operand" ""))]
The "" is not needed.
> + "FLOAT128_IEEE_P (<MODE>mode)"
> +{
> + if (TARGET_FLOAT128_HW)
> + emit_insn (gen_copysign<mode>3_hard (operands[0], operands[1],
> + operands[2]));
Tabbing here...
> + else
> + {
> + rtx tmp = gen_reg_rtx (<MODE>mode);
> + emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1],
> + operands[2], tmp));
... and here is completely broken.
> @@ -13336,6 +13354,18 @@
> "xscpsgnqp %0,%2,%1"
> [(set_attr "type" "vecsimple")])
>
> +(define_insn "copysign<mode>3_soft"
> + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
> + (unspec:IEEE128
> + [(match_operand:IEEE128 1 "altivec_register_operand" "v")
> + (match_operand:IEEE128 2 "altivec_register_operand" "v")
> + (match_operand:IEEE128 3 "altivec_register_operand" "+v")]
> + UNSPEC_COPYSIGN))]
> + "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
> + "xscpsgndp %x3,%x2,%x1\n\txxpermdi %x0,%x3,%x1,1"
Two machine insns in a template should be separated by \; not \n\t .
> +Additional built-in functions are available for the 64-bit PowerPC
> +family of processors, for efficient use of 128-bit floating point
> +(@code{__float128}) values.
> +
> +The following floating-point built-in functions are always available. All
> +of them implement the function that is part of the name.
"Always"? Not just with -mfloat128? And it needs VMX?
Segher
