On Fri, Apr 22, 2016 at 03:35:42PM +0000, Wilco Dijkstra wrote:
> SIMD operations like combine prefer to have their operands in FP registers,
> so increase the cost of integer registers slightly to avoid unnecessary
> int<->FP moves. This improves register allocation of scalar SIMD operations.
I really don't like [1][2][3] this technique of attempting to work around
register allocator issues using the disparaging mechanisms.
If we take this, our set of patterns using disparaging becomes:
aarch64_combinez
aarch64_combinez_be
aarch64_simd_mov
movhf_aarch64
movsf_aarch64
movdf_aarch64
movtf_aarch64
xor_one_cmpl
So doing this would be in line with other move operations, but is still
a workaround to deeper issues.
The patch is OK, on that justification, but I'd like not to set a
precedent for using "?" rather than looking to find the underlying issue.
Thanks,
James
---
[1] Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.
https://gcc.gnu.org/ml/gcc-patches/2014-03/msg01627.html
[2] Re: [PATCH AArch64 1/3] Don't disparage add/sub in SIMD registers
https://gcc.gnu.org/ml/gcc-patches/2014-08/msg01332.html
[3] Re: [PATCH AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for
BIC,ORN,EON
https://gcc.gnu.org/ml/gcc-patches/2014-08/msg01278.html
>
> OK for trunk?
>
> ChangeLog:
> 2016-04-22 Wilco Dijkstra <wdijk...@arm.com>
>
> * gcc/config/aarch64/aarch64-simd.md (aarch64_combinez):
> Add ? to integer variant.
> (aarch64_combinez_be): Likewise.
>
> --
>
