Similar as [3/6], these intrinsics were implemented before the instruction
pattern "aarch64_rsqrts<mode>" added, that these intrinsics were implemented
through inline assembly.
This mirgrate the implementation to builtin.
gcc/
2016-05-23 Jiong Wang <jiong.w...@arm.com>
* config/aarch64/aarch64-builtins.def (rsqrts): New builtins
for modes
VALLF.
* config/aarch64/aarch64-simd.md (aarch64_rsqrts_<mode>3):
Rename to
"aarch64_rsqrts<mode>".
* config/aarch64/aarch64.c (get_rsqrts_type): Update gen* name.
* config/aarch64/arm_neon.h (vrsqrtss_f32): Remove inline
assembly. Use
builtin.
(vrsqrtsd_f64): Likewise.
(vrsqrts_f32): Likewise.
(vrsqrtsq_f32): Likewise.
(vrsqrtsq_f64): Likewise.
>From ea271deeb19e3a1e611cbc1ddf3abfec06388958 Mon Sep 17 00:00:00 2001
From: "Jiong.Wang" <jiong.w...@arm.com>
Date: Mon, 23 May 2016 12:12:33 +0100
Subject: [PATCH 4/6] 4
---
gcc/config/aarch64/aarch64-builtins.def | 3 ++
gcc/config/aarch64/aarch64-simd.md | 2 +-
gcc/config/aarch64/aarch64.c | 10 ++--
gcc/config/aarch64/arm_neon.h | 87 ++++++++++++---------------------
4 files changed, 41 insertions(+), 61 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-builtins.def b/gcc/config/aarch64/aarch64-builtins.def
index 32bcd06..1955d17 100644
--- a/gcc/config/aarch64/aarch64-builtins.def
+++ b/gcc/config/aarch64/aarch64-builtins.def
@@ -462,3 +462,6 @@
/* Implemented by aarch64_rsqrte<mode>. */
BUILTIN_VALLF (UNOP, rsqrte, 0)
+
+ /* Implemented by aarch64_rsqrts<mode>. */
+ BUILTIN_VALLF (BINOP, rsqrts, 0)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index c34d21e..cca6c1b 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -390,7 +390,7 @@
"frsqrte\\t%<v>0<Vmtype>, %<v>1<Vmtype>"
[(set_attr "type" "neon_fp_rsqrte_<Vetype><q>")])
-(define_insn "aarch64_rsqrts_<mode>3"
+(define_insn "aarch64_rsqrts<mode>"
[(set (match_operand:VALLF 0 "register_operand" "=w")
(unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w")
(match_operand:VALLF 2 "register_operand" "w")]
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 18a8c1e..ba71d2a 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -7377,11 +7377,11 @@ get_rsqrts_type (machine_mode mode)
{
switch (mode)
{
- case DFmode: return gen_aarch64_rsqrts_df3;
- case SFmode: return gen_aarch64_rsqrts_sf3;
- case V2DFmode: return gen_aarch64_rsqrts_v2df3;
- case V2SFmode: return gen_aarch64_rsqrts_v2sf3;
- case V4SFmode: return gen_aarch64_rsqrts_v4sf3;
+ case DFmode: return gen_aarch64_rsqrtsdf;
+ case SFmode: return gen_aarch64_rsqrtssf;
+ case V2DFmode: return gen_aarch64_rsqrtsv2df;
+ case V2SFmode: return gen_aarch64_rsqrtsv2sf;
+ case V4SFmode: return gen_aarch64_rsqrtsv4sf;
default: gcc_unreachable ();
}
}
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index be48a5e..1971373 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -9196,61 +9196,6 @@ vrsqrteq_u32 (uint32x4_t a)
return result;
}
-__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-vrsqrts_f32 (float32x2_t a, float32x2_t b)
-{
- float32x2_t result;
- __asm__ ("frsqrts %0.2s,%1.2s,%2.2s"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float64_t __attribute__ ((__always_inline__))
-vrsqrtsd_f64 (float64_t a, float64_t b)
-{
- float64_t result;
- __asm__ ("frsqrts %d0,%d1,%d2"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-vrsqrtsq_f32 (float32x4_t a, float32x4_t b)
-{
- float32x4_t result;
- __asm__ ("frsqrts %0.4s,%1.4s,%2.4s"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
-vrsqrtsq_f64 (float64x2_t a, float64x2_t b)
-{
- float64x2_t result;
- __asm__ ("frsqrts %0.2d,%1.2d,%2.2d"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
-__extension__ static __inline float32_t __attribute__ ((__always_inline__))
-vrsqrtss_f32 (float32_t a, float32_t b)
-{
- float32_t result;
- __asm__ ("frsqrts %s0,%s1,%s2"
- : "=w"(result)
- : "w"(a), "w"(b)
- : /* No clobbers */);
- return result;
-}
-
#define vshrn_high_n_s16(a, b, c) \
__extension__ \
({ \
@@ -21481,6 +21426,38 @@ vrsqrteq_f64 (float64x2_t a)
return __builtin_aarch64_rsqrtev2df (a);
}
+/* vrsqrts. */
+
+__extension__ static __inline float32_t __attribute__ ((__always_inline__))
+vrsqrtss_f32 (float32_t a, float32_t b)
+{
+ return __builtin_aarch64_rsqrtssf (a, b);
+}
+
+__extension__ static __inline float64_t __attribute__ ((__always_inline__))
+vrsqrtsd_f64 (float64_t a, float64_t b)
+{
+ return __builtin_aarch64_rsqrtsdf (a, b);
+}
+
+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+vrsqrts_f32 (float32x2_t a, float32x2_t b)
+{
+ return __builtin_aarch64_rsqrtsv2sf (a, b);
+}
+
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vrsqrtsq_f32 (float32x4_t a, float32x4_t b)
+{
+ return __builtin_aarch64_rsqrtsv4sf (a, b);
+}
+
+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+vrsqrtsq_f64 (float64x2_t a, float64x2_t b)
+{
+ return __builtin_aarch64_rsqrtsv2df (a, b);
+}
+
/* vrsra */
__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
--
1.9.1
