Hello!
I was looking at recent g++.dg/ext/sync-4.C testsuite FAILure on
alpha-linux-gnu. The testcase installs SIGSEGV handler and among other
tests, it does various tests with atomic operations on NULL addresses.
One test (f19):
FN(19, void, (__atomic_exchange((ditype*)p, (ditype*)0, (ditype*)0,
__ATOMIC_SEQ_CST)))
expands to following initial RTX sequence:
5: r71:DI=0
6: r70:DI=[r71:DI]
7: {trap_if 0x1;use $29:DI;}
8: barrier
where _.sched2 pass is free to reorder insns from
6: $1:DI=[0]
REG_UNUSED $1:DI
7: {trap_if 0x1;use $29:DI;}
REG_DEAD $29:DI
8: barrier
to:
7: {trap_if 0x1;use $29:DI;}
REG_DEAD $29:DI
6: $1:DI=[0]
REG_UNUSED $1:DI
8: barrier
resulting in:
$ ./a.out
Trace/breakpoint trap
Please note that handler is able to recover from SIGSEGV, but not from
SIGTRAP. If these two signals are reordered, the testcase fails.
Proposed patch solves this issue by also forcing pending loads to
memory. This way, memory access is ordered with trap insn, and the
testcase passes.
2016-05-19 Uros Bizjak <ubiz...@gmail.com>
* sched-deps.c (sched_analyze_2) <case TRAP_IF>: Also
force pending loads from memory.
Patch was bootstrapped and regression tested on alphaev68-linux-gnu
and x86_64-linux-gnu {,-m32}.
OK for mainline and release branches?
Uros.
Index: sched-deps.c
===================================================================
--- sched-deps.c (revision 236461)
+++ sched-deps.c (working copy)
@@ -2709,9 +2709,12 @@ sched_analyze_2 (struct deps_desc *deps, rtx x, rt
return;
}
- /* Force pending stores to memory in case a trap handler needs them. */
+ /* Force pending stores to memory in case a trap handler needs them.
+ Also force pending loads from memory; loads and stores can segfault
+ and the signal handler won't be triggered if the trap insn was moved
+ above load or store insn. */
case TRAP_IF:
- flush_pending_lists (deps, insn, true, false);
+ flush_pending_lists (deps, insn, true, true);
break;
case PREFETCH:
