Hi!
vpalignr is AVX512BW & VL, so we shouldn't enable it just for VL.
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2016-05-13 Jakub Jelinek <ja...@redhat.com>
* config/i386/sse.md (<ssse3_avx2>_palignr<mode>): Use
constraint x instead of v in second alternative, add avx512bw
alternative.
* gcc.target/i386/avx512vl-vpalignr-3.c: New test.
* gcc.target/i386/avx512bw-vpalignr-3.c: New test.
--- gcc/config/i386/sse.md.jj 2016-05-13 15:47:50.978978445 +0200
+++ gcc/config/i386/sse.md 2016-05-13 16:12:24.631965207 +0200
@@ -14289,11 +14289,11 @@ (define_insn "<ssse3_avx2>_palignr<mode>
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<ssse3_avx2>_palignr<mode>"
- [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,v")
+ [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,x,v")
(unspec:SSESCALARMODE
- [(match_operand:SSESCALARMODE 1 "register_operand" "0,v")
- (match_operand:SSESCALARMODE 2 "vector_operand" "xBm,vm")
- (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")]
+ [(match_operand:SSESCALARMODE 1 "register_operand" "0,x,v")
+ (match_operand:SSESCALARMODE 2 "vector_operand" "xBm,xm,vm")
+ (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n,n")]
UNSPEC_PALIGNR))]
"TARGET_SSSE3"
{
@@ -14304,18 +14304,19 @@ (define_insn "<ssse3_avx2>_palignr<mode>
case 0:
return "palignr\t{%3, %2, %0|%0, %2, %3}";
case 1:
+ case 2:
return "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}";
default:
gcc_unreachable ();
}
}
- [(set_attr "isa" "noavx,avx")
+ [(set_attr "isa" "noavx,avx,avx512bw")
(set_attr "type" "sseishft")
(set_attr "atom_unit" "sishuf")
- (set_attr "prefix_data16" "1,*")
+ (set_attr "prefix_data16" "1,*,*")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
- (set_attr "prefix" "orig,vex")
+ (set_attr "prefix" "orig,vex,evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "ssse3_palignrdi"
--- gcc/testsuite/gcc.target/i386/avx512vl-vpalignr-3.c.jj 2016-05-13
16:10:56.071176218 +0200
+++ gcc/testsuite/gcc.target/i386/avx512vl-vpalignr-3.c 2016-05-13
16:11:30.292708261 +0200
@@ -0,0 +1,30 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */
+
+#include <x86intrin.h>
+
+void
+f1 (__m128i x, __m128i y)
+{
+ register __m128i a __asm ("xmm16"), b __asm ("xmm17");
+ a = x;
+ b = y;
+ asm volatile ("" : "+v" (a), "+v" (b));
+ a = _mm_alignr_epi8 (a, b, 3);
+ asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler-not "vpalignr\[^\n\r]*xmm1\[67]" } } */
+
+void
+f2 (__m256i x, __m256i y)
+{
+ register __m256i a __asm ("xmm16"), b __asm ("xmm17");
+ a = x;
+ b = y;
+ asm volatile ("" : "+v" (a), "+v" (b));
+ a = _mm256_alignr_epi8 (a, b, 3);
+ asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler-not "vpalignr\[^\n\r]*ymm1\[67]" } } */
--- gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-3.c.jj 2016-05-13
16:10:35.332459807 +0200
+++ gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-3.c 2016-05-13
16:09:23.000000000 +0200
@@ -0,0 +1,30 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw" } */
+
+#include <x86intrin.h>
+
+void
+f1 (__m128i x, __m128i y)
+{
+ register __m128i a __asm ("xmm16"), b __asm ("xmm17");
+ a = x;
+ b = y;
+ asm volatile ("" : "+v" (a), "+v" (b));
+ a = _mm_alignr_epi8 (a, b, 3);
+ asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler
"vpalignr\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" } } */
+
+void
+f2 (__m256i x, __m256i y)
+{
+ register __m256i a __asm ("xmm16"), b __asm ("xmm17");
+ a = x;
+ b = y;
+ asm volatile ("" : "+v" (a), "+v" (b));
+ a = _mm256_alignr_epi8 (a, b, 3);
+ asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler
"vpalignr\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]" } } */
Jakub
