Hi!

Another insn where we can just unconditionally use v constraint instead of x
- for V2DImode HARD_REGNO_MODE_OK will only allow it for AVX512VL for the
ext regs, the insn is actually already available in AVX512F, but probably
not worth spending too much time on this to allow it even for xmm16-xmm31
for -mavx512f -mno-avx512vl.

Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?

2016-05-03  Jakub Jelinek  <ja...@redhat.com>

        * config/i386/sse.md (sse2_movq128): Use v constraint instead of x.

        * gcc.target/i386/avx512vl-vmovq-1.c: New test.

--- gcc/config/i386/sse.md.jj   2016-05-03 00:12:09.210351372 +0200
+++ gcc/config/i386/sse.md      2016-05-03 10:04:41.560546790 +0200
@@ -1076,10 +1076,10 @@ (define_insn "<avx512>_store<mode>_mask"
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "sse2_movq128"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
+  [(set (match_operand:V2DI 0 "register_operand" "=v")
        (vec_concat:V2DI
          (vec_select:DI
-           (match_operand:V2DI 1 "nonimmediate_operand" "xm")
+           (match_operand:V2DI 1 "nonimmediate_operand" "vm")
            (parallel [(const_int 0)]))
          (const_int 0)))]
   "TARGET_SSE2"
--- gcc/testsuite/gcc.target/i386/avx512vl-vmovq-1.c.jj 2016-05-03 
10:09:20.930749746 +0200
+++ gcc/testsuite/gcc.target/i386/avx512vl-vmovq-1.c    2016-05-03 
10:10:40.673665926 +0200
@@ -0,0 +1,16 @@
+/* { dg-do assemble { target { avx512vl && { ! ia32 } } } } */
+/* { dg-options "-O2 -mavx512vl" } */
+
+#include <x86intrin.h>
+
+void
+foo (__m128i x, __m128i *y)
+{
+  register __m128i a __asm ("xmm16");
+  a = x;
+  asm volatile ("" : "+v" (a));
+  a = _mm_move_epi64 (a);
+  asm volatile ("" : "+v" (a));
+  a = _mm_move_epi64 (*y);
+  asm volatile ("" : "+v" (a));
+}

        Jakub

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