On Tue, 26 Apr 2016, Jeff Law wrote: > > So offhand I think you need an RTL instruction splitter to express this, > > and then avoid fetching 64 bits worth of data from memory -- for the sake > > of matching the indexed addressing mode -- where you only need 32 bits. > > At the hardware instruction level I'd use a scratch register (as with > > MOVAQ you'd have to waste one anyway) to scale the index and then use > > MOVAL instead with the modified index. Where no index is used it gets > > simpler even as you can just bump up the displacement according to the > > subreg offset. > Note you shouldn't need an expander for this. > > That insn is just a 32bit load. I would have expected something to simplify > the subreg expression, likely requiring loading the address into a register in > the process.
Hmm, producing a MOVAQ/MOVL sequence (rather than fiddling with the index register) will ensure any increment/decrement mode works just fine. This observation also makes me agree with you in that we should always just load the result of the original address expression somewhere; likely a register, but on a VAX it could well be memory (though the indirect address mode is not offsettable; not in the sense perhaps needed here), so maybe we don't have to restrict that. Maciej
