On Thu, Apr 21, 2016 at 3:18 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
> On Thu, Apr 21, 2016 at 9:42 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
>> On Thu, Apr 21, 2016 at 9:37 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
>>> On Wed, Apr 20, 2016 at 9:53 PM, H.J. Lu <hongjiu...@intel.com> wrote:
>>>> Since all 1s in TImode is standard SSE2 constants, all 1s in OImode is
>>>> standard AVX2 constants and all 1s in XImode is standard AVX512F constants,
>>>> pass mode to standard_sse_constant_p and standard_sse_constant_opcode
>>>> to check if all 1s is available for target.
>>>>
>>>> Tested on Linux/x86-64. OK for master?
>>>
>>> No.
>>>
>>> This patch should use "isa" attribute instead of adding even more
>>> similar patterns. Also, please leave MEM_P checks, the rare C->m move
>>> can be easily resolved by IRA.
>>
>> Actually, register_operand checks are indeed better, please disregard
>> MEM_P recommendation.
>
> So, something like attached untested RFC proto-patch, that lacks
> wide-int handling.
>
> Uros.
+
+ else if (CONST_INT_P (x))
+ {
+ if (INTVAL (X) == HOST_WIDE_INT_M1
+ && TARGET_SSE2)
+ return 2;
+ }
+ else if (CONST_WIDE_INT_P (x))
+ {
+ if (.... something involving wi::minus-one ....
+ && TARGET_AVX2)
+ return 2;
+ if (....
+ && TARGET_AVX512F)
+ return 2;
+ }
+ else if (vector_all_ones_operand (x, mode))
All 1s may not use winde_int. It has VOIDmode.
The mode is passed by
@@ -18758,7 +18771,7 @@ ix86_expand_vector_move (machine_mode mode,
rtx operands[])
&& (CONSTANT_P (op1)
|| (SUBREG_P (op1)
&& CONSTANT_P (SUBREG_REG (op1))))
- && !standard_sse_constant_p (op1))
+ && !standard_sse_constant_p (op1, mode))
op1 = validize_mem (force_const_mem (mode, op1));
This is why I have
-standard_sse_constant_p (rtx x)
+standard_sse_constant_p (rtx x, machine_mode mode)
{
- machine_mode mode;
-
if (!TARGET_SSE)
return 0;
- mode = GET_MODE (x);
-
+ if (mode == VOIDmode)
+ mode = GET_MODE (x);
+
since all 1s `x' may have VOIDmode when called from
ix86_expand_vector_move if mode isn't passed.
--
H.J.
