Hello,
Patch in the bottom fixes mentioned PR by separating
AVX and AVX-512BW constraints.
gcc/
* gcc/config/i386/sse.md (define_insn "<shift_insn><mode>3<mask_name>"):
Extract AVX-512BW constraint from AVX.
gcc/testsuite/
* gcc.target/i386/pr70728.c: New test.
Bootsrap and regtest is in progress for i?86|x86_64.
I'll check it into main trunk if it'll pass.
--
Thanks, K
commit c98976fc83f62c1faf1d7e3302632fa084e4cc60
Author: Kirill Yukhin <kirill.yuk...@intel.com>
Date: Thu Apr 21 12:59:38 2016 +0300
AVX-512. Fir PR target/70728 by adding explicit constraint for EVEX.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 9a84468..48a7abb 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -10138,22 +10138,23 @@
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<shift_insn><mode>3<mask_name>"
- [(set (match_operand:VI48_AVX2 0 "register_operand" "=x,v")
+ [(set (match_operand:VI48_AVX2 0 "register_operand" "=x,x,v")
(any_lshift:VI48_AVX2
- (match_operand:VI48_AVX2 1 "register_operand" "0,v")
- (match_operand:SI 2 "nonmemory_operand" "xN,vN")))]
+ (match_operand:VI48_AVX2 1 "register_operand" "0,x,v")
+ (match_operand:SI 2 "nonmemory_operand" "xN,xN,vN")))]
"TARGET_SSE2 && <mask_mode512bit_condition>"
"@
p<vshift><ssemodesuffix>\t{%2, %0|%0, %2}
- vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>,
%1, %2}"
- [(set_attr "isa" "noavx,avx")
+ vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>,
%1, %2}
+ vp<vshift><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>,
%1, %2}"
+ [(set_attr "isa" "noavx,avx,avx512bw")
(set_attr "type" "sseishft")
(set (attr "length_immediate")
(if_then_else (match_operand 2 "const_int_operand")
(const_string "1")
(const_string "0")))
- (set_attr "prefix_data16" "1,*")
- (set_attr "prefix" "orig,vex")
+ (set_attr "prefix_data16" "1,*,*")
+ (set_attr "prefix" "orig,vex,evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<shift_insn><mode>3<mask_name>"
diff --git a/gcc/testsuite/gcc.target/i386/pr70728.c
b/gcc/testsuite/gcc.target/i386/pr70728.c
new file mode 100644
index 0000000..89c140d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70728.c
@@ -0,0 +1,30 @@
+/* PR target/70728 */
+/* { dg-do compile } */
+/* { dg-options "-S -Ofast -march=knl" } */
+
+short a = -15726;
+int b = (int)-7003557328690506537LL;
+short c[5][5][3][6];
+char d[2][5][3][2][4];
+void fn1() {
+ for (int e = 0; e < 3; e = e + 1)
+ for (int f = 0; f < 2; f = f + 1)
+ for (int g = 0; g < 4; g = g + 1)
+ for (int h = 0; h < 3; h = h + 1)
+ for (int i = 0; i < 2; i = i + 1)
+ for (int j = 0; j < 4; j = j + 1)
+ d[f][g][h][i][j] =
+ 7 << (1236110361944357083 >> a + 15728) - 309027590486089270
>>
+ (c[e][f][h][j] + 2147483647 << ~b - 7003557328690506536) -
+ 2147480981;
+}
+int main() {
+ for (int k = 0; k < 5; ++k)
+ for (int l = 0; l < 5; ++l)
+ for (int m = 0; m < 3; ++m)
+ for (int n = 0; n < 4; ++n)
+ c[k][l][m][n] = -2639;
+ fn1();
+}
+
+/* { dg-final { scan-assembler-not "sll\[
\\t\]+\[^\n\]*%\.mm(?:1\[6-9\]|\[2-3\]\[0-9\])" } } */
