On 16 March 2016 at 16:54, Ramana Radhakrishnan <ramana....@googlemail.com> wrote: > On Wed, Feb 24, 2016 at 11:23 AM, Kyrill Tkachov > <kyrylo.tkac...@foss.arm.com> wrote: >> Hi all, >> >> This is the GCC 4.9 backport of >> https://gcc.gnu.org/ml/gcc-patches/2016-02/msg01338.html. >> The differences are that TARGET_HAVE_LPAE has to be defined in arm.h in a >> different way because >> the ARM_FSET_HAS_CPU1 mechanism doesn't exist on this branch. Also, due to >> the location of insn_flags >> and the various FL_* (on the 4.9 branch they're defined locally in arm.c >> rather than in arm-protos.h) >> I chose to define TARGET_HAVE_LPAE in terms of hardware divide instruction >> availability. This should be >> an equivalent definition. >> >> Also, the scan-assembler tests that check for the DMB instruction are >> updated to check for >> "dmb sy" rather than "dmb ish", because the memory barrier instruction >> changed on trunk for GCC 6. >> >> Bootstrapped and tested on the GCC 4.9 branch on arm-none-linux-gnueabihf. >> >> >> Ok for the branch after the trunk patch has had a few days to bake? > > > OK. > Hi Kyrylo,
Since you backported this to branches 4.9 and 5, I've noticed cross-GCC build failures: --target arm-none-linux-gnueabihf --with-mode=arm --with-cpu=cortex-a57 --with-fpu=crypto-neon-fp-armv8 The build succeeds --with-mode=thumb. The error message I'm seeing is: /tmp/6190285_22.tmpdir/ccuX17sh.s: Assembler messages: /tmp/6190285_22.tmpdir/ccuX17sh.s:34: Error: bad instruction `ldrdeq r0,r1,[r0]' make[4]: *** [load_8_.lo] Error 1 while building libatomic Christophe > Ramana >> >> Thanks, >> Kyrill >> >> 2016-02-24 Kyrylo Tkachov <kyrylo.tkac...@arm.com> >> >> PR target/69875 >> * config/arm/arm.h (TARGET_HAVE_LPAE): Define. >> * config/arm/unspecs.md (VUNSPEC_LDRD_ATOMIC): New value. >> * config/arm/sync.md (arm_atomic_loaddi2_ldrd): New pattern. >> (atomic_loaddi_1): Delete. >> (atomic_loaddi): Rewrite expander using the above changes. >> >> 2016-02-24 Kyrylo Tkachov <kyrylo.tkac...@arm.com> >> >> PR target/69875 >> * gcc.target/arm/atomic_loaddi_acquire.x: New file. >> * gcc.target/arm/atomic_loaddi_relaxed.x: Likewise. >> * gcc.target/arm/atomic_loaddi_seq_cst.x: Likewise. >> * gcc.target/arm/atomic_loaddi_1.c: New test. >> * gcc.target/arm/atomic_loaddi_2.c: Likewise. >> * gcc.target/arm/atomic_loaddi_3.c: Likewise. >> * gcc.target/arm/atomic_loaddi_4.c: Likewise. >> * gcc.target/arm/atomic_loaddi_5.c: Likewise. >> * gcc.target/arm/atomic_loaddi_6.c: Likewise. >> * gcc.target/arm/atomic_loaddi_7.c: Likewise. >> * gcc.target/arm/atomic_loaddi_8.c: Likewise. >> * gcc.target/arm/atomic_loaddi_9.c: Likewise.
