With this patch the substitution patterns added earlier are used for
the logical right shift and all the left shift patterns.
* config/s390/s390.md ("<shift><mode>3"): Change predicate of
op2 to nonmemory_operand.
("*<shift>di3_31", "*<shift>di3_31_and"):
Merge into single pattern definition ...
("*<shift>di3_31<addr_style_op><masked_op>"): New pattern.
("*<shift><mode>3", "*<shift><mode>3_and"): Merge into single
pattern definition ...
("*<shift><mode>3<addr_style_op><masked_op>"): New pattern.
---
gcc/config/s390/s390.md | 63 ++++++++++++++++++-------------------------------
1 file changed, 23 insertions(+), 40 deletions(-)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 9703a30..b4983cd 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -8395,60 +8395,43 @@
(define_expand "<shift><mode>3"
[(set (match_operand:DSI 0 "register_operand" "")
(SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
+ (match_operand:SI 2 "nonmemory_operand" "")))]
""
"")
+; ESA 64 bit register pair shift with reg or imm shift count
; sldl, srdl
-(define_insn "*<shift>di3_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
+(define_insn "*<shift>di3_31<addr_style_op><masked_op>"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (SHIFT:DI (match_operand:DI 1 "register_operand" "0,0")
+ (match_operand:SI 2 "nonmemory_operand" "a,n")))]
"!TARGET_ZARCH"
- "s<lr>dl\t%0,%Y2"
+ "@
+ s<lr>dl\t%0,<addr_style_op_op3>(%2)
+ s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")
+ (set_attr "enabled" "*,<addr_style_op_enabled>")
(set_attr "z196prop" "z196_cracked")])
-; sll, srl, sllg, srlg, sllk, srlk
-(define_insn "*<shift><mode>3"
- [(set (match_operand:GPR 0 "register_operand"
"=d,d")
- (SHIFT:GPR (match_operand:GPR 1 "register_operand"
"<d0>,d")
- (match_operand:SI 2 "shift_count_or_setmem_operand"
"Y,Y")))]
- ""
- "@
- s<lr>l<g>\t%0,<1>%Y2
- s<lr>l<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
-
-; sldl, srdl
-(define_insn "*<shift>di3_31_and"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand"
"Y")
- (match_operand:SI 3 "const_int_operand" "n"))))]
- "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
- "s<lr>dl\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
+; 64 bit register shift with reg or imm shift count
; sll, srl, sllg, srlg, sllk, srlk
-(define_insn "*<shift><mode>3_and"
- [(set (match_operand:GPR 0 "register_operand"
"=d,d")
- (SHIFT:GPR (match_operand:GPR 1 "register_operand"
"<d0>,d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand"
"Y,Y")
- (match_operand:SI 3 "const_int_operand"
"n,n"))))]
- "(INTVAL (operands[3]) & 63) == 63"
+(define_insn "*<shift><mode>3<addr_style_op><masked_op>"
+ [(set (match_operand:GPR 0 "register_operand" "=d, d,d,d")
+ (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,<d0>,d,d")
+ (match_operand:SI 2 "nonmemory_operand" "a, n,a,n")))]
+ ""
"@
+ s<lr>l<g>\t%0,<1><addr_style_op_op3>(%2)
s<lr>l<g>\t%0,<1>%Y2
+ s<lr>l<gk>\t%0,%1,<addr_style_op_op3>(%2)
s<lr>l<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
+ [(set_attr "op_type" "RS<E>,RS<E>,RSY,RSY")
+ (set_attr "atype" "reg,reg,reg,reg")
+ (set_attr "cpu_facility" "*,*,z196,z196")
+ (set_attr "enabled" "*,<addr_style_op_enabled>,*,<addr_style_op_enabled>")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
;
; ashr(di|si)3 instruction pattern(s).
--
1.9.1
