Hi!
As I wrote in the PR, fwprop is able to forward CONST0_RTX back into
instructions even if CSE optimized them, but the problem in that case is
that for vector_move_operand "0C" operands if they appear inside of
(vec_select ... (parallel [(const_int 0) ... ])) the result is also
simplified, so one gets instead another CONST0_RTX (in the mode of
the VEC_SELECT). Because the patterns expect a vec_select and "C" operand
inside of it, it is therefore not matched, it maybe attached as REG_EQUAL
note. I went through other vector_move_operand "0C" and "0C,0" operands
and I don't think they suffer from similar problem, if fwprop or cprop etc.
attempts to propagate a constant into them, it shouldn't be possible it will
be simplified into something different.
Anyway, the fix IMHO is to just duplicate the affected 8 define_insns
with the simplification applied. IMHO once we know it is {z}, it is worth
to keep it as {z}, there is no benefit to allow the RA to use "0"
operand instead.
Bootstrapped/regtested on x86_64-linux and i686-linux, on both fixes
the testcases that started failing with r233133, ok for trunk?
2016-02-17 Jakub Jelinek <ja...@redhat.com>
PR target/69671
* config/i386/sse.md (*<floatsuffix>floatv2div2sf2_mask_1,
*avx512vl_<code>v2div2qi2_mask_1, *avx512vl_<code><mode>v4qi2_mask_1,
*avx512vl_<code><mode>v8qi2_mask_1, *avx512vl_<code><mode>v4hi2_mask_1,
*avx512vl_<code>v2div2hi2_mask_1, *avx512vl_<code>v2div2si2_mask_1,
*avx512f_<code>v8div16qi2_mask_1): New insns.
--- gcc/config/i386/sse.md.jj 2016-02-15 22:22:46.000000000 +0100
+++ gcc/config/i386/sse.md 2016-02-17 12:25:50.528896579 +0100
@@ -4962,6 +4962,21 @@ (define_insn "<floatsuffix>floatv2div2sf
(set_attr "prefix" "evex")
(set_attr "mode" "V4SF")])
+(define_insn "*<floatsuffix>floatv2div2sf2_mask_1"
+ [(set (match_operand:V4SF 0 "register_operand" "=v")
+ (vec_concat:V4SF
+ (vec_merge:V2SF
+ (any_float:V2SF (match_operand:V2DI 1
+ "nonimmediate_operand" "vm"))
+ (const_vector:V2SF [(const_int 0) (const_int 0)])
+ (match_operand:QI 2 "register_operand" "Yk"))
+ (const_vector:V2SF [(const_int 0) (const_int 0)])))]
+ "TARGET_AVX512DQ && TARGET_AVX512VL"
+ "vcvt<floatsuffix>qq2ps{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
+ [(set_attr "type" "ssecvt")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "V4SF")])
+
(define_insn "ufloat<si2dfmodelower><mode>2<mask_name>"
[(set (match_operand:VF2_512_256VL 0 "register_operand" "=v")
(unsigned_float:VF2_512_256VL
@@ -9150,6 +9165,27 @@ (define_insn "avx512vl_<code>v2div2qi2_m
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
+(define_insn "*avx512vl_<code>v2div2qi2_mask_1"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (vec_concat:V16QI
+ (vec_merge:V2QI
+ (any_truncate:V2QI
+ (match_operand:V2DI 1 "register_operand" "v"))
+ (const_vector:V2QI [(const_int 0) (const_int 0)])
+ (match_operand:QI 2 "register_operand" "Yk"))
+ (const_vector:V14QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])))]
+ "TARGET_AVX512VL"
+ "vpmov<trunsuffix>qb\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
+
(define_insn "avx512vl_<code>v2div2qi2_mask_store"
[(set (match_operand:V16QI 0 "memory_operand" "=m")
(vec_concat:V16QI
@@ -9219,6 +9255,27 @@ (define_insn "avx512vl_<code><mode>v4qi2
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
+(define_insn "*avx512vl_<code><mode>v4qi2_mask_1"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (vec_concat:V16QI
+ (vec_merge:V4QI
+ (any_truncate:V4QI
+ (match_operand:VI4_128_8_256 1 "register_operand" "v"))
+ (const_vector:V4QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])
+ (match_operand:QI 2 "register_operand" "Yk"))
+ (const_vector:V12QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])))]
+ "TARGET_AVX512VL"
+ "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
+
(define_insn "avx512vl_<code><mode>v4qi2_mask_store"
[(set (match_operand:V16QI 0 "memory_operand" "=m")
(vec_concat:V16QI
@@ -9289,6 +9346,27 @@ (define_insn "avx512vl_<code><mode>v8qi2
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
+(define_insn "*avx512vl_<code><mode>v8qi2_mask_1"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (vec_concat:V16QI
+ (vec_merge:V8QI
+ (any_truncate:V8QI
+ (match_operand:VI2_128_BW_4_256 1 "register_operand" "v"))
+ (const_vector:V8QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])
+ (match_operand:QI 2 "register_operand" "Yk"))
+ (const_vector:V8QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])))]
+ "TARGET_AVX512VL"
+ "vpmov<trunsuffix><pmov_suff_3>\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
+
(define_insn "avx512vl_<code><mode>v8qi2_mask_store"
[(set (match_operand:V16QI 0 "memory_operand" "=m")
(vec_concat:V16QI
@@ -9370,6 +9448,23 @@ (define_insn "avx512vl_<code><mode>v4hi2
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
+(define_insn "*avx512vl_<code><mode>v4hi2_mask_1"
+ [(set (match_operand:V8HI 0 "register_operand" "=v")
+ (vec_concat:V8HI
+ (vec_merge:V4HI
+ (any_truncate:V4HI
+ (match_operand:VI4_128_8_256 1 "register_operand" "v"))
+ (const_vector:V4HI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])
+ (match_operand:QI 2 "register_operand" "Yk"))
+ (const_vector:V4HI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])))]
+ "TARGET_AVX512VL"
+ "vpmov<trunsuffix><pmov_suff_4>\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
+
(define_insn "avx512vl_<code><mode>v4hi2_mask_store"
[(set (match_operand:V8HI 0 "memory_operand" "=m")
(vec_concat:V8HI
@@ -9428,6 +9523,23 @@ (define_insn "avx512vl_<code>v2div2hi2_m
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
+(define_insn "*avx512vl_<code>v2div2hi2_mask_1"
+ [(set (match_operand:V8HI 0 "register_operand" "=v")
+ (vec_concat:V8HI
+ (vec_merge:V2HI
+ (any_truncate:V2HI
+ (match_operand:V2DI 1 "register_operand" "v"))
+ (const_vector:V2HI [(const_int 0) (const_int 0)])
+ (match_operand:QI 2 "register_operand" "Yk"))
+ (const_vector:V6HI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])))]
+ "TARGET_AVX512VL"
+ "vpmov<trunsuffix>qw\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
+
(define_insn "avx512vl_<code>v2div2hi2_mask_store"
[(set (match_operand:V8HI 0 "memory_operand" "=m")
(vec_concat:V8HI
@@ -9494,6 +9606,21 @@ (define_insn "avx512vl_<code>v2div2si2_m
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
+(define_insn "*avx512vl_<code>v2div2si2_mask_1"
+ [(set (match_operand:V4SI 0 "register_operand" "=v")
+ (vec_concat:V4SI
+ (vec_merge:V2SI
+ (any_truncate:V2SI
+ (match_operand:V2DI 1 "register_operand" "v"))
+ (const_vector:V2SI [(const_int 0) (const_int 0)])
+ (match_operand:QI 2 "register_operand" "Yk"))
+ (const_vector:V2SI [(const_int 0) (const_int 0)])))]
+ "TARGET_AVX512VL"
+ "vpmov<trunsuffix>qd\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
+
(define_insn "avx512vl_<code>v2div2si2_mask_store"
[(set (match_operand:V4SI 0 "memory_operand" "=m")
(vec_concat:V4SI
@@ -9569,6 +9696,27 @@ (define_insn "avx512f_<code>v8div16qi2_m
[(set_attr "type" "ssemov")
(set_attr "prefix" "evex")
(set_attr "mode" "TI")])
+
+(define_insn "*avx512f_<code>v8div16qi2_mask_1"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (vec_concat:V16QI
+ (vec_merge:V8QI
+ (any_truncate:V8QI
+ (match_operand:V8DI 1 "register_operand" "v"))
+ (const_vector:V8QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])
+ (match_operand:QI 2 "register_operand" "Yk"))
+ (const_vector:V8QI [(const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)
+ (const_int 0) (const_int 0)])))]
+ "TARGET_AVX512F"
+ "vpmov<trunsuffix>qb\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
(define_insn "avx512f_<code>v8div16qi2_mask_store"
[(set (match_operand:V16QI 0 "memory_operand" "=m")
Jakub
