Re: [PATCH, rs6000] Fix pasto resulting in wrong instruction from builtins for lvxl

[Bill Schmidt]

On Tue, 2016-02-16 at 11:40 -0800, David Edelsohn wrote:
> This is okay, but how about starting with a testcase for this? 

Fair enough.  Here's the revised patch with a test, which I've verified
on powerpc64-unknown-linux-gnu.  Ok to proceed?

Thanks!

Bill


[gcc]

2016-02-16  Bill Schmidt  <wschm...@linux.vnet.ibm.com>

        * config/rs6000/altivec.md (*altivec_lvxl_<mode>_internal): Output
        correct instruction.

[gcc/testsuite]

2012-02-16  Bill Schmidt  <wschm...@linux.vnet.ibm.com>

        * gcc.target/powerpc/vec-cg.c: New test.


Index: gcc/config/rs6000/altivec.md
===================================================================
--- gcc/config/rs6000/altivec.md        (revision 233466)
+++ gcc/config/rs6000/altivec.md        (working copy)
@@ -2511,7 +2511,7 @@
          (match_operand:VM2 1 "memory_operand" "Z"))
      (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
   "TARGET_ALTIVEC"
-  "lvx %0,%y1"
+  "lvxl %0,%y1"
   [(set_attr "type" "vecload")])
 
 (define_expand "altivec_lvx_<mode>"
Index: gcc/testsuite/gcc.target/powerpc/vec-cg.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-cg.c   (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/vec-cg.c   (working copy)
@@ -0,0 +1,22 @@
+/* Test code generation of vector built-ins.  We don't have this for
+   most of ours today.  As new built-ins are added, please add to this
+   test case.  Update as necessary to add VSX, P8-vector, P9-vector,
+   etc. */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O0" } */
+
+#include <altivec.h>
+
+static vector signed int i, *pi;
+static int int1;
+
+void
+b()
+{
+  i = __builtin_altivec_lvxl (int1, pi);
+  i = vec_lvxl (int1, pi);
+}
+
+/* { dg-final { scan-assembler-times "lvxl" 2 } } */