Hans-Peter Nilsson schrieb:
On Thu, 11 Aug 2011, Georg-Johann Lay wrote:
This is an optimization in machine dependent reorg to
remove redundant comparisons like in
cc0 = compare (Reg, Num)
if (cc0 == 0)
goto L1
cc0 = compare (Reg, Num)
if (cc0 > 0)
goto L2
The second comparison is redundant an can be removed.
Code like this can be seen in binary decision switch/case
expansion.
A glance at AVR makes me think this should already be handled by
the NOTICE_UPDATE_CC machinery. Any analysis why this doesn't
happen? With the same test-case (at -Os) I don't see redundant
compares for cris-elf, for example.
One reason is that branch insns set cc0 to "clobber" where it is
actually "none". I could not depict the rationale for this from
the avr BE, presumably it's because of text peepholes that change
branches or jump-over-one-insn skip optimizations.
Second reason is that avr has no GT/GTU and therefore reorg transforms
cc0 = compare (Reg, Num)
if (cc0 > 0)
goto L2
to
cc0 = compare (Reg, Num-1)
if (cc0 >= 0)
goto L2
so that the comparisons are no more the same.
Of cource, reorg could ommit the last optimization if there is
a similar comparison beforehand. But the hard part is not
doing/skipping the optimization, the annoyance is detecting the
right 4-insn instruction sequences.
I also thought about extending genrecog et al. which currently
can handle 3 types of things (RECOG, SPLIT, PEEPHOLE2) to a
fourth one like INSN_SEQ so that one could write down the
sequence as RTL instead of as brain-dead C (brain-dead in the
way it must be written down, not in what it does)
and use insn-recog, insn-extract etc. to analyse such sequences.
This might also be helpful in other backends when doing similar
optimizations or writing hand-coded schedulers or when scanning
for specific sequences to work around core errata.
Johann
brgds, H-P
