Hello!
Attached patch corrects "C" constraint to accept only SSE constant
zero operand and introduces new "BC" constraint to accept all SSE
constant operands (all bits 0 and all bits 1).
As discussed in the PR, the compiler ICEs when "C" constraint is used
non-zero vector operands, so it is still possible to change the
constraint a bit. With fixed constraint, we get "impossible
constraint" error instead of ICEing when following testcase:
--cut here--
typedef int __v4si __attribute__ ((__vector_size__ (16)));
void test (void)
{
asm volatile ("%0" : : "C" ( (__v4si) { -1, -1, -1, -1 } ));
}
--cut here--
is compiled with -O2 -msse2.
2016-01-28 Uros Bizjak <ubiz...@gmail.com>
PR target/69459
* config/i386/constraints.md (C): Only accept constant zero operand.
(BC): New constraint.
* config/i386/sse.md (*mov<mode>_internal): Use BC constraint
instead of C constraint.
* doc/md.texi (Machine Constraints): Update description
of C constraint.
testsuite/ChangeLog:
2016-01-28 Uros Bizjak <ubiz...@gmail.com>
PR target/69459
* gcc.target/i386/pr69459.c: New test.
Patch was bootstrapped and regression tested on x86_64-linux-gnu
{,-m32}. Patch was committed to mainline SVN and will be backported to
release branches.
Uros.
Index: config/i386/constraints.md
===================================================================
--- config/i386/constraints.md (revision 232929)
+++ config/i386/constraints.md (working copy)
@@ -152,6 +152,7 @@
;; s Sibcall memory operand, not valid for TARGET_X32
;; w Call memory operand, not valid for TARGET_X32
;; z Constant call address operand.
+;; C SSE constant operand.
(define_constraint "Bf"
"@internal Flags register operand."
@@ -183,6 +184,10 @@
"@internal Constant call address operand."
(match_operand 0 "constant_call_address_operand"))
+(define_constraint "BC"
+ "@internal SSE constant operand."
+ (match_test "standard_sse_constant_p (op)"))
+
;; Integer constant constraints.
(define_constraint "I"
"Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
@@ -233,8 +238,8 @@
;; This can theoretically be any mode's CONST0_RTX.
(define_constraint "C"
- "Standard SSE floating point constant."
- (match_test "standard_sse_constant_p (op)"))
+ "SSE constant zero operand."
+ (match_test "standard_sse_constant_p (op) == 1"))
;; Constant-or-symbol-reference constraints.
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md (revision 232929)
+++ config/i386/sse.md (working copy)
@@ -833,7 +833,7 @@
(define_insn "*mov<mode>_internal"
[(set (match_operand:VMOVE 0 "nonimmediate_operand" "=v,v ,m")
- (match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" "C ,vm,v"))]
+ (match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" "BC,vm,v"))]
"TARGET_SSE
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
Index: doc/md.texi
===================================================================
--- doc/md.texi (revision 232929)
+++ doc/md.texi (working copy)
@@ -4100,7 +4100,7 @@ Integer constant in the range 0 @dots{} 127, for 1
Standard 80387 floating point constant.
@item C
-Standard SSE floating point constant.
+SSE constant zero operand.
@item e
32-bit signed integer constant, or a symbolic reference known
Index: testsuite/gcc.target/i386/pr69459.c
===================================================================
--- testsuite/gcc.target/i386/pr69459.c (nonexistent)
+++ testsuite/gcc.target/i386/pr69459.c (working copy)
@@ -0,0 +1,42 @@
+/* PR target/69549 */
+/* { dg-do run { target sse2_runtime } } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned int u32;
+typedef unsigned long long u64;
+typedef unsigned char v16u8 __attribute__ ((vector_size (16)));
+typedef unsigned short v16u16 __attribute__ ((vector_size (16)));
+typedef unsigned int v16u32 __attribute__ ((vector_size (16)));
+typedef unsigned long long v16u64 __attribute__ ((vector_size (16)));
+
+u64 __attribute__((noinline, noclone))
+foo (u8 u8_0, u16 u16_3, v16u8 v16u8_0, v16u16 v16u16_0, v16u32 v16u32_0,
v16u64 v16u64_0, v16u8 v16u8_1, v16u16 v16u16_1, v16u32 v16u32_1, v16u64
v16u64_1, v16u8 v16u8_2, v16u16 v16u16_2, v16u32 v16u32_2, v16u64 v16u64_2,
v16u8 v16u8_3, v16u16 v16u16_3, v16u32 v16u32_3, v16u64 v16u64_3)
+{
+ v16u64_0 /= (v16u64){u16_3, ((0))} | 1;
+ v16u64_1 += (v16u64)~v16u32_0;
+ v16u16_1 /= (v16u16){-v16u64_3[1]} | 1;
+ v16u64_3[1] -= 0x1fffffff;
+ v16u32_2 /= (v16u32)-v16u64_0 | 1;
+ v16u32_1 += ~v16u32_1;
+ v16u16_3 %= (v16u16){0xfff, v16u32_2[3], v16u8_0[14]} | 1;
+ v16u64_3 -= (v16u64)v16u32_2;
+ if (v16u64_1[1] >= 1) {
+ v16u64_0 %= (v16u64){v16u32_0[1]} | 1;
+ v16u32_1[1] %= 0x5fb856;
+ v16u64_1 |= -v16u64_0;
+ }
+ v16u8_0 *= (v16u8)v16u32_1;
+ return u8_0 + v16u8_0 [12] + v16u8_0 [13] + v16u8_0 [14] + v16u8_0 [15] +
v16u16_0 [0] + v16u16_0 [1] + v16u32_0 [0] + v16u32_0 [1] + v16u32_0 [2] +
v16u32_0 [3] + v16u64_0 [0] + v16u64_0 [1] + v16u8_1 [9] + v16u8_1 [10] +
v16u8_1 [11] + v16u8_1 [15] + v16u16_1 [0] + v16u16_1 [1] + v16u16_1 [3] +
v16u64_1 [0] + v16u64_1 [1] + v16u8_2 [3] + v16u8_2 [4] + v16u8_2 [5] + v16u8_2
[0] + v16u32_2 [1] + v16u32_2 [2] + v16u32_2 [3] + v16u64_2 [0] + v16u64_2 [1]
+ v16u8_3 [0] + v16u16_3 [6] + v16u16_3[7] + v16u32_3[1] + v16u32_3[2] +
v16u64_3[0] + v16u64_3[1];
+}
+
+int
+main ()
+{
+ u64 x = foo(1, 1, (v16u8){1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
(v16u16){1, 1}, (v16u32){1}, (v16u64){1}, (v16u8){1}, (v16u16){1, 1},
(v16u32){1}, (v16u64){1}, (v16u8){1, 1, 1, 1, 1}, (v16u16){1}, (v16u32){1},
(v16u64){1}, (v16u8){1}, (v16u16){1}, (v16u32){1}, (v16u64){1});
+
+ if (x != 0xffffffffe0000209)
+ __builtin_abort();
+ return 0;
+}
