On Thu, Dec 31, 2015 at 1:30 PM, Michael Meissner <meiss...@linux.vnet.ibm.com> wrote: > This patch adds support for the ISA 3.0 XXPERM instruction, which is like > VPERM, except it can operate on any VSX register. Since the instruction is a > 3 > operand instruction (RT and RA must be the same), I made it so VPERM was > preferred. I also added XXPERM fusion support where a XXLOR move instruction > immediately before the XXPERM instruction is fused together. > > I have bootstrapped and done make check on a big endian power7 and a little > endian power8 system. In addition, I built all of Spec 2006 with power9 > support enabled, and all of the tests that previously built now build with > XXPERM being generated (the OMNETPP benchmark currently does not build on > little endian for either power8 or power9). Are these patches ok to check in? > > [gcc] > 2015-12-31 Michael Meissner <meiss...@linux.vnet.ibm.com> > > * config/rs6000/constraints.md (wo constraint): New constraint for > ISA 3.0 (power9). > > * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add support > for wo constraint. > (rs6000_init_hard_regno_mode_ok): Likewise. > > * config/rs6000/rs6000.h (r6000_reg_class_enum): Add support for > wo constraint. > > * config/rs6000/altivec.md (altivec_vperm_<mode>): Clean up vperm > expanders not to have constraints. Add support for ISA 3.0 xxperm > instruction. Add support for fusing xxlor with xxperm. > (altivec_vperm_<mode>_internal): Likewise. > (altivec_vperm_v8hiv16qi): Likewise. > (altivec_vperm_<mode>v16q): Likewise. > (altivec_vperm_<mode>_uns): Likewise. > (vperm_v8hiv4si): Likewise. > (vperm_v16qiv8hi): Likewise. > > * doc/md.texi (RS/6000 constraints): Document wo constraint. > > [gcc/testsuite] > 2015-12-31 Michael Meissner <meiss...@linux.vnet.ibm.com> > > * gcc.target/powerpc/p9-permute.c: New test for xxperm code > generation.
This is okay. Thanks, David
