Ping.
https://gcc.gnu.org/ml/gcc-patches/2015-12/msg00708.html
Thanks,
Kyrill
On 07/12/15 10:39, Kyrill Tkachov wrote:
Hi all,
In this PR we ICE because during post-reload splitting we generate the insn:
(insn 27 26 11 2 (set (reg:SI 0 r0 [orig:121 D.4992 ] [121])
(and:SI (not:SI (const_int 1 [0x1]))
(reg:SI 0 r0 [orig:121 D.4992 ] [121])))
(nil))
The splitter at fault is andsi_iorsi3_notsi that accepts a const_int in
operands[3]
and outputs (not (match_dup 3)). It should really be trying to constant fold
the result
first. This patch does that by calling simplify_gen_unary to generate the
complement
of operands[3] if it's a register or the appropriate const_int rtx with the
correct
folded result that will still properly match the arm bic-immediate instruction.
Bootstrapped and tested on arm-none-eabi.
Is this ok for trunk?
This appears on GCC 4.9 and GCC 5 and I'll be testing the fix there as well.
Ok for those branches if testing is successful?
Thanks,
Kyrill
2015-12-07 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
PR target/68648
* config/arm/arm.md (*andsi_iorsi3_notsi): Try to simplify
the complement of operands[3] during splitting.
2015-12-07 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
PR target/68648
* gcc.c-torture/execute/pr68648.c: New test.
