The attached fixes an ICE building gridengine. The problem is we are asked to
do an HImode reload
for a floating pointing register. However, we can only do 32 and 64-bit loads
and stores to/from floating
point registers.
The problem is resolved by not checking that the mode requested is consistent
with the modes of the
input and output operands.
Tested on hppa-unknown-linux-gnu, hppa2.0w-hp-hpux11.11 and
hppa64-hp-hpux11.11. Committed
to trunk and active branches.
Dave
--
John David Anglin dave.ang...@bell.net
2015-12-09 John David Anglin <dang...@gcc.gnu.org>
PR target/68729
* config/pa/pa.c (pa_emit_move_sequence): Don't check that mode is
consistent with modes of the input and output operands when doing
reloads to and from floating point registers. Do reload for all
address forms.
Index: config/pa/pa.c
===================================================================
--- config/pa/pa.c (revision 231326)
+++ config/pa/pa.c (working copy)
@@ -1683,11 +1683,10 @@
REG+D addresses where D does not fit in 5 or 14 bits, including
(subreg (mem (addr))) cases. */
if (scratch_reg
- && fp_reg_operand (operand0, mode)
+ && FP_REG_P (operand0)
&& (MEM_P (operand1)
|| (GET_CODE (operand1) == SUBREG
- && MEM_P (XEXP (operand1, 0))))
- && !floating_point_store_memory_operand (operand1, mode))
+ && MEM_P (XEXP (operand1, 0)))))
{
if (GET_CODE (operand1) == SUBREG)
operand1 = XEXP (operand1, 0);
@@ -1699,10 +1698,8 @@
/* D might not fit in 14 bits either; for such cases load D into
scratch reg. */
- if (reg_plus_base_memory_operand (operand1, mode)
- && !(TARGET_PA_20
- && !TARGET_ELF32
- && INT_14_BITS (XEXP (XEXP (operand1, 0), 1))))
+ if (reg_plus_base_memory_operand (operand1, GET_MODE (operand1))
+ && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)))
{
emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
emit_move_insn (scratch_reg,
@@ -1718,11 +1715,10 @@
return 1;
}
else if (scratch_reg
- && fp_reg_operand (operand1, mode)
+ && FP_REG_P (operand1)
&& (MEM_P (operand0)
|| (GET_CODE (operand0) == SUBREG
- && MEM_P (XEXP (operand0, 0))))
- && !floating_point_store_memory_operand (operand0, mode))
+ && MEM_P (XEXP (operand0, 0)))))
{
if (GET_CODE (operand0) == SUBREG)
operand0 = XEXP (operand0, 0);
@@ -1734,10 +1730,8 @@
/* D might not fit in 14 bits either; for such cases load D into
scratch reg. */
- if (reg_plus_base_memory_operand (operand0, mode)
- && !(TARGET_PA_20
- && !TARGET_ELF32
- && INT_14_BITS (XEXP (XEXP (operand0, 0), 1))))
+ if (reg_plus_base_memory_operand (operand0, GET_MODE (operand0))
+ && !INT_14_BITS (XEXP (XEXP (operand0, 0), 1)))
{
emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
