[PATCH, i386, PR68627] Prohibit AVX-512VL broadcasts generation on KNL.

[Kirill Yukhin]

Hello,
Patch in the bottom fixes spec2k6/437.leslie3d illigal insn generation.
The problem is that for AVX-512F broacasts are allowed to 512b registers only.
[x|y]mm variants are AVX-512VL.

Bootstrapped and regtested.

I'll commit it into GCC main trunk on Monday if no objections.

gcc/
        PR target/68627
        * config/i386/sse.md: Make 'v' alternative work on 'avx512f' ISA only.
        Force destination to 512 bits register.

gcc/testsuite/
        PR target/68627
        * gfortran.dg/pr68627.f: New test.

--
Thanks, K

commit ff93d08d61d58c28707b224f5b84ab30628b34a3
Author: Kirill Yukhin <kirill.yuk...@intel.com>
Date:   Tue Dec 1 10:28:17 2015 +0300

    AVX-512. Make broadcast from SSE reg AVX-512 only. Force to zmm.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e7b517a..0286e6b 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -17377,20 +17377,21 @@
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "vec_dup<mode>"
-  [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "=x,x,v,x")
+  [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "=x,x,x,v,x")
        (vec_duplicate:AVX_VEC_DUP_MODE
-         (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "m,m,v,?x")))]
+         (match_operand:<ssescalarmode> 1 "nonimmediate_operand" 
"m,m,x,v,?x")))]
   "TARGET_AVX"
   "@
    v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0|%0, %1}
    vbroadcast<ssescalarmodesuffix>\t{%1, %0|%0, %1}
    v<sseintprefix>broadcast<bcstscalarsuff>\t{%x1, %0|%0, %x1}
+   v<sseintprefix>broadcast<bcstscalarsuff>\t{%x1, %g0|%g0, %x1}
    #"
   [(set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "maybe_evex")
-   (set_attr "isa" "avx2,noavx2,avx2,noavx2")
-   (set_attr "mode" "<sseinsnmode>,V8SF,<sseinsnmode>,V8SF")])
+   (set_attr "isa" "avx2,noavx2,avx2,avx512f,noavx2")
+   (set_attr "mode" "<sseinsnmode>,V8SF,<sseinsnmode>,<sseinsnmode>,V8SF")])
 
 (define_split
   [(set (match_operand:AVX2_VEC_DUP_MODE 0 "register_operand")
diff --git a/gcc/testsuite/gfortran.dg/pr68627.f 
b/gcc/testsuite/gfortran.dg/pr68627.f
new file mode 100755
index 0000000..32ff4a7
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr68627.f
@@ -0,0 +1,18 @@
+! { dg-do compile { target lp64 } }
+
+! { dg-options "-Ofast -mavx512f -ffixed-xmm1 -ffixed-xmm2 -ffixed-xmm3 
-ffixed-xmm4 -ffixed-xmm5 -ffixed-xmm6 -ffixed-xmm7 -ffixed-xmm8 -ffixed-xmm9 
-ffixed-xmm10 -ffixed-xmm11 -ffixed-xmm12 -ffixed-xmm13 -ffixed-xmm14 
-ffixed-xmm15" }
+
+      IMPLICIT REAL*8(A-H,O-Z)
+      ALLOCATABLE DD1(:), DD2(:), WY(:,:)
+      ALLOCATE( DD1(MAX), DD2(MAX), WY(MAX,MAX))
+         DO J = J1,J2
+            DO I = I1, I2
+               DD1(I) = D1 * (WY(I-2,J) - WY(I+2,J) +
+     >              (WY(I+1,J) - WY(I-1,J)))
+            END DO
+            DO I = I1, INT(D2 * D3(I))
+            END DO
+         END DO
+      END
+
+! { dg-final { scan-assembler-not "vbroadcastsd\[ \\t\]+%xmm\[0-9\]+, 
%ymm\[0-9\]+" } }