Tested as described in the covering note. I plan to commit this as obvious
if the prerequisites are approved.
gcc/
* config/mips/mips.md (move_type): Turn into a code,alternative
attribute.
(mode, dword_mode, compression, enabled): Likewise.
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index d24dcfe..2f8dfbd 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -223,14 +223,16 @@
"unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove,
const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
shift_shift"
- (const_string "unknown"))
+ (const_string "unknown")
+ "code,alternative")
(define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"
(const_string "unknown"))
;; Main data type used by the insn
(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
- (const_string "unknown"))
+ (const_string "unknown")
+ "code,alternative")
;; True if the main data type is twice the size of a word.
(define_attr "dword_mode" "no,yes"
@@ -241,7 +243,8 @@
(and (eq_attr "mode" "TI,TF")
(match_test "TARGET_64BIT"))
(const_string "yes")]
- (const_string "no")))
+ (const_string "no"))
+ "code,alternative")
;; Attributes describing a sync loop. These loops have the form:
;;
@@ -441,7 +444,8 @@
(const_string "no")))
(define_attr "compression" "none,all,micromips32,micromips"
- (const_string "none"))
+ (const_string "none")
+ "code,alternative")
(define_attr "enabled" "no,yes"
(cond [;; The o32 FPXX and FP64A ABI extensions prohibit direct moves between
@@ -454,7 +458,8 @@
(and (eq_attr "compression" "micromips32,micromips")
(match_test "!TARGET_MICROMIPS"))
(const_string "no")]
- (const_string "yes")))
+ (const_string "yes"))
+ "code,alternative")
;; The number of individual instructions that a non-branch pattern generates,
;; using units of BASE_INSN_LENGTH.
