The "enabled" attribute is supposed to be an invariant property of an
alternative and shouldn't depend on having access to a particular insn.
Although I think the port honours that, it's not really enforceable at
compile time because "enabled" depends on "length", which in turn requires
access to an insn in order to calculate branch lengths. This patch
introduces a second attribute to indicate whether a single-instruction
pattern is 16-bit or not.
Tested as described in the covering note.
gcc/
* config/nds32/nd32.md (is_16bit): New attribute.
(length, enabled): Use it.
(*mov<mode>): Use "is_16bit" instead of "length".
(*sethi, *lo_sum, zero_extend<mode>si2, extend<mode>si2, add<mode>3)
(sub<mode>3, *add_slli, *add_srli, *sub_slli, *sub_srli, mulsi3)
(mulsidi3, umulsidi3, *maddr32_0, *maddr32_1, *msubr32, divmodsi4)
(udivmodsi4, bitc, andsi3, *and_slli, *and_srli, iorsi3, *or_slli)
(*or_srli, xorsi3, *xor_slli, *xor_srli, rotrsi3, negsi2)
(one_cmplsi2, ashlsi3, ashrsi3, lshrsi3, cmovz, cmovn, slts_compare)
(slt_compare, indirect_jump, *call_register, *call_value_register)
(*sibcall_register, *sibcall_value_register, clzsi2, smaxsi3)
(sminsi3, *btst): Likewise.
diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md
index 3dc1ce8..89c0391 100644
--- a/gcc/config/nds32/nds32.md
+++ b/gcc/config/nds32/nds32.md
@@ -56,8 +56,15 @@
(const_string "unknown"))
+;; True if the instruction requires TARGET_16_BIT.
+(define_attr "is_16bit" "no,yes" (const_string "no"))
+
+
;; Length, in bytes, default is 4-bytes.
-(define_attr "length" "" (const_int 4))
+(define_attr "length" ""
+ (cond [(eq_attr "is_16bit" "yes")
+ (const_int 2)]
+ (const_int 4)))
;; Enabled, which is used to enable/disable insn alternatives.
@@ -66,7 +73,7 @@
;; determine the length by itself, its enabled attribute should be
;; always 1 to avoid the conflict with the settings here.
(define_attr "enabled" ""
- (cond [(and (eq_attr "length" "2")
+ (cond [(and (eq_attr "is_16bit" "yes")
(match_test "!TARGET_16_BIT"))
(const_int 0)]
(const_int 1)))
@@ -169,8 +176,8 @@
gcc_unreachable ();
}
}
- [(set_attr "type"
"alu,alu,store,store,store,store,store,load,load,load,load,load,alu,alu,alu,alu")
- (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2,
2, 4, 2, 2, 4, 4")])
+ [(set_attr "type"
"alu,alu,store,store,store,store,store,load,load,load,load,load,alu,alu,alu,alu")
+ (set_attr "is_16bit" "yes, no, yes, yes, yes, yes, no, yes, yes, yes,
yes, no,yes,yes, no, no")])
;; We use nds32_symbolic_operand to limit that only CONST/SYMBOL_REF/LABEL_REF
@@ -190,7 +197,7 @@
""
"sethi\t%0, hi20(%1)"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
(define_insn "*lo_sum"
@@ -200,7 +207,7 @@
""
"ori\t%0, %1, lo12(%2)"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
;; ----------------------------------------------------------------------------
@@ -227,8 +234,8 @@
gcc_unreachable ();
}
}
- [(set_attr "type" "alu,alu,load,load")
- (set_attr "length" " 2, 4, 2, 4")])
+ [(set_attr "type" "alu,alu,load,load")
+ (set_attr "is_16bit" "yes, no, yes, no")])
;; Sign extension instructions.
@@ -251,8 +258,8 @@
gcc_unreachable ();
}
}
- [(set_attr "type" "alu,alu,load")
- (set_attr "length" " 2, 4, 4")])
+ [(set_attr "type" "alu,alu,load")
+ (set_attr "is_16bit" "yes, no, no")])
;; ----------------------------------------------------------------------------
@@ -298,8 +305,8 @@
gcc_unreachable ();
}
}
- [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
- (set_attr "length" " 2, 2, 2, 2, 2, 2, 2, 2, 4, 4")])
+ [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
+ (set_attr "is_16bit" "yes,yes,yes,yes,yes,yes,yes,yes, no, no")])
(define_insn "sub<mode>3"
[(set (match_operand:QIHISI 0 "register_operand" "=d, l,
r, r")
@@ -311,8 +318,8 @@
sub333\t%0, %1, %2
subri\t%0, %2, %1
sub\t%0, %1, %2"
- [(set_attr "type" "alu,alu,alu,alu")
- (set_attr "length" " 2, 2, 4, 4")])
+ [(set_attr "type" "alu,alu,alu,alu")
+ (set_attr "is_16bit" "yes,yes, no, no")])
;; GCC intends to simplify (plus (ashift ...) (reg))
@@ -334,7 +341,7 @@
return "add_slli\t%0, %3, %1, %2";
}
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
(define_insn "*add_srli"
[(set (match_operand:SI 0 "register_operand" "= r")
@@ -344,7 +351,7 @@
"TARGET_ISA_V3"
"add_srli\t%0, %3, %1, %2"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
;; GCC intends to simplify (minus (reg) (ashift ...))
@@ -366,7 +373,7 @@
return "sub_slli\t%0, %1, %2, %3";
}
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
(define_insn "*sub_srli"
[(set (match_operand:SI 0 "register_operand" "= r")
@@ -376,7 +383,7 @@
"TARGET_ISA_V3"
"sub_srli\t%0, %1, %2, %3"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
;; Multiplication instructions.
@@ -389,8 +396,8 @@
"@
mul33\t%0, %2
mul\t%0, %1, %2"
- [(set_attr "type" "alu,alu")
- (set_attr "length" " 2, 4")])
+ [(set_attr "type" "alu,alu")
+ (set_attr "is_16bit" "yes, no")])
(define_insn "mulsidi3"
[(set (match_operand:DI 0 "register_operand" "=r")
@@ -398,8 +405,8 @@
(sign_extend:DI (match_operand:SI 2 "register_operand" "
r"))))]
"TARGET_ISA_V2 || TARGET_ISA_V3"
"mulsr64\t%0, %1, %2"
- [(set_attr "type" "alu")
- (set_attr "length" "4")])
+ [(set_attr "type" "alu")
+ (set_attr "is_16bit" "no")])
(define_insn "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "=r")
@@ -407,8 +414,8 @@
(zero_extend:DI (match_operand:SI 2 "register_operand" "
r"))))]
"TARGET_ISA_V2 || TARGET_ISA_V3"
"mulr64\t%0, %1, %2"
- [(set_attr "type" "alu")
- (set_attr "length" "4")])
+ [(set_attr "type" "alu")
+ (set_attr "is_16bit" "no")])
;; Multiply-accumulate instructions.
@@ -420,8 +427,8 @@
(match_operand:SI 2 "register_operand" " r"))))]
""
"maddr32\t%0, %1, %2"
- [(set_attr "type" "alu")
- (set_attr "length" "4")])
+ [(set_attr "type" "alu")
+ (set_attr "is_16bit" "no")])
(define_insn "*maddr32_1"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -430,8 +437,8 @@
(match_operand:SI 3 "register_operand" " 0")))]
""
"maddr32\t%0, %1, %2"
- [(set_attr "type" "alu")
- (set_attr "length" "4")])
+ [(set_attr "type" "alu")
+ (set_attr "is_16bit" "no")])
(define_insn "*msubr32"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -440,8 +447,8 @@
(match_operand:SI 2 "register_operand" " r"))))]
""
"msubr32\t%0, %1, %2"
- [(set_attr "type" "alu")
- (set_attr "length" "4")])
+ [(set_attr "type" "alu")
+ (set_attr "is_16bit" "no")])
;; Div Instructions.
@@ -454,8 +461,8 @@
(mod:SI (match_dup 1) (match_dup 2)))]
""
"divsr\t%0, %3, %1, %2"
- [(set_attr "type" "alu")
- (set_attr "length" "4")])
+ [(set_attr "type" "alu")
+ (set_attr "is_16bit" "no")])
(define_insn "udivmodsi4"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -465,8 +472,8 @@
(umod:SI (match_dup 1) (match_dup 2)))]
""
"divr\t%0, %3, %1, %2"
- [(set_attr "type" "alu")
- (set_attr "length" "4")])
+ [(set_attr "type" "alu")
+ (set_attr "is_16bit" "no")])
;; ----------------------------------------------------------------------------
@@ -485,8 +492,7 @@
"TARGET_ISA_V3"
"bitc\t%0, %2, %1"
[(set_attr "type" "alu")
- (set_attr "length" "4")]
-)
+ (set_attr "is_16bit" "no")])
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=w, r, l, l,
l, l, l, l, r, r, r, r, r")
@@ -554,8 +560,8 @@
gcc_unreachable ();
}
}
- [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
- (set_attr "length" " 2, 4, 2, 2, 2, 2, 2, 2, 4, 4, 4, 4, 4")])
+ [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
+ (set_attr "is_16bit" "yes, no,yes,yes,yes,yes,yes,yes, no, no, no, no,
no")])
(define_insn "*and_slli"
[(set (match_operand:SI 0 "register_operand" "= r")
@@ -565,7 +571,7 @@
"TARGET_ISA_V3"
"and_slli\t%0, %3, %1, %2"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
(define_insn "*and_srli"
[(set (match_operand:SI 0 "register_operand" "= r")
@@ -575,7 +581,7 @@
"TARGET_ISA_V3"
"and_srli\t%0, %3, %1, %2"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
;; ----------------------------------------------------------------------------
@@ -614,8 +620,8 @@
gcc_unreachable ();
}
}
- [(set_attr "type" "alu,alu,alu,alu")
- (set_attr "length" " 2, 4, 4, 4")])
+ [(set_attr "type" "alu,alu,alu,alu")
+ (set_attr "is_16bit" "yes, no, no, no")])
(define_insn "*or_slli"
[(set (match_operand:SI 0 "register_operand" "= r")
@@ -625,7 +631,7 @@
"TARGET_ISA_V3"
"or_slli\t%0, %3, %1, %2"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
(define_insn "*or_srli"
[(set (match_operand:SI 0 "register_operand" "= r")
@@ -635,7 +641,7 @@
"TARGET_ISA_V3"
"or_srli\t%0, %3, %1, %2"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
;; ----------------------------------------------------------------------------
@@ -674,8 +680,8 @@
gcc_unreachable ();
}
}
- [(set_attr "type" "alu,alu,alu,alu")
- (set_attr "length" " 2, 4, 4, 4")])
+ [(set_attr "type" "alu,alu,alu,alu")
+ (set_attr "is_16bit" "yes, no, no, no")])
(define_insn "*xor_slli"
[(set (match_operand:SI 0 "register_operand" "= r")
@@ -685,7 +691,7 @@
"TARGET_ISA_V3"
"xor_slli\t%0, %3, %1, %2"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
(define_insn "*xor_srli"
[(set (match_operand:SI 0 "register_operand" "= r")
@@ -695,7 +701,7 @@
"TARGET_ISA_V3"
"xor_srli\t%0, %3, %1, %2"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
;; Rotate Right Instructions.
@@ -707,8 +713,8 @@
"@
rotri\t%0, %1, %2
rotr\t%0, %1, %2"
- [(set_attr "type" "alu,alu")
- (set_attr "length" " 4, 4")])
+ [(set_attr "type" "alu,alu")
+ (set_attr "is_16bit" " no, no")])
;; ----------------------------------------------------------------------------
@@ -726,8 +732,8 @@
"@
neg33\t%0, %1
subri\t%0, %1, 0"
- [(set_attr "type" "alu,alu")
- (set_attr "length" " 2, 4")])
+ [(set_attr "type" "alu,alu")
+ (set_attr "is_16bit" "yes, no")])
;; ----------------------------------------------------------------------------
@@ -743,8 +749,8 @@
"@
not33\t%0, %1
nor\t%0, %1, %1"
- [(set_attr "type" "alu,alu")
- (set_attr "length" " 2, 4")])
+ [(set_attr "type" "alu,alu")
+ (set_attr "is_16bit" "yes, no")])
;; ----------------------------------------------------------------------------
@@ -760,8 +766,8 @@
slli333\t%0, %1, %2
slli\t%0, %1, %2
sll\t%0, %1, %2"
- [(set_attr "type" "alu,alu,alu")
- (set_attr "length" " 2, 4, 4")])
+ [(set_attr "type" "alu,alu,alu")
+ (set_attr "is_16bit" "yes, no, no")])
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "= d, r, r")
@@ -772,8 +778,8 @@
srai45\t%0, %2
srai\t%0, %1, %2
sra\t%0, %1, %2"
- [(set_attr "type" "alu,alu,alu")
- (set_attr "length" " 2, 4, 4")])
+ [(set_attr "type" "alu,alu,alu")
+ (set_attr "is_16bit" "yes, no, no")])
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "= d, r, r")
@@ -784,8 +790,8 @@
srli45\t%0, %2
srli\t%0, %1, %2
srl\t%0, %1, %2"
- [(set_attr "type" "alu,alu,alu")
- (set_attr "length" " 2, 4, 4")])
+ [(set_attr "type" "alu,alu,alu")
+ (set_attr "is_16bit" "yes, no, no")])
;; ----------------------------------------------------------------------------
@@ -921,7 +927,7 @@ create_template:
cmovz\t%0, %2, %1
cmovn\t%0, %3, %1"
[(set_attr "type" "move")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
(define_insn "cmovn"
[(set (match_operand:SI 0 "register_operand" "=r, r")
@@ -934,7 +940,7 @@ create_template:
cmovn\t%0, %2, %1
cmovz\t%0, %3, %1"
[(set_attr "type" "move")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
;; ----------------------------------------------------------------------------
@@ -1827,8 +1833,8 @@ create_template:
sltsi45\t%1, %2
slts\t%0, %1, %2
sltsi\t%0, %1, %2"
- [(set_attr "type" "compare,compare,compare,compare")
- (set_attr "length" " 2, 2, 4, 4")])
+ [(set_attr "type" "compare,compare,compare,compare")
+ (set_attr "is_16bit" " yes, yes, no, no")])
(define_insn "slt_compare"
[(set (match_operand:SI 0 "register_operand" "=t, t, r, r")
@@ -1840,8 +1846,8 @@ create_template:
slti45\t%1, %2
slt\t%0, %1, %2
slti\t%0, %1, %2"
- [(set_attr "type" "compare,compare,compare,compare")
- (set_attr "length" " 2, 2, 4, 4")])
+ [(set_attr "type" "compare,compare,compare,compare")
+ (set_attr "is_16bit" " yes, yes, no, no")])
;; ----------------------------------------------------------------------------
@@ -1889,8 +1895,8 @@ create_template:
"@
jr5\t%0
jr\t%0"
- [(set_attr "type" "branch,branch")
- (set_attr "length" " 2, 4")])
+ [(set_attr "type" "branch,branch")
+ (set_attr "is_16bit" " yes, no")])
;; Subroutine call instruction returning no value.
;; operands[0]: It should be a mem RTX whose address is
@@ -1916,8 +1922,8 @@ create_template:
"@
jral5\t%0
jral\t%0"
- [(set_attr "type" "branch,branch")
- (set_attr "length" " 2, 4")])
+ [(set_attr "type" "branch,branch")
+ (set_attr "is_16bit" " yes, no")])
(define_insn "*call_immediate"
[(parallel [(call (mem (match_operand:SI 0 "immediate_operand" "i"))
@@ -1964,8 +1970,8 @@ create_template:
"@
jral5\t%1
jral\t%1"
- [(set_attr "type" "branch,branch")
- (set_attr "length" " 2, 4")])
+ [(set_attr "type" "branch,branch")
+ (set_attr "is_16bit" " yes, no")])
(define_insn "*call_value_immediate"
[(parallel [(set (match_operand 0)
@@ -2013,8 +2019,8 @@ create_template:
"@
jr5\t%0
jr\t%0"
- [(set_attr "type" "branch,branch")
- (set_attr "length" " 2, 4")])
+ [(set_attr "type" "branch,branch")
+ (set_attr "is_16bit" " yes, no")])
(define_insn "*sibcall_immediate"
[(parallel [(call (mem (match_operand:SI 0 "immediate_operand" "i"))
@@ -2058,8 +2064,8 @@ create_template:
"@
jr5\t%1
jr\t%1"
- [(set_attr "type" "branch,branch")
- (set_attr "length" " 2, 4")])
+ [(set_attr "type" "branch,branch")
+ (set_attr "is_16bit" " yes, no")])
(define_insn "*sibcall_value_immediate"
[(parallel [(set (match_operand 0)
@@ -2341,7 +2347,7 @@ create_template:
"TARGET_PERF_EXT"
"clz\t%0, %1"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
(define_insn "smaxsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -2350,7 +2356,7 @@ create_template:
"TARGET_PERF_EXT"
"max\t%0, %1, %2"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
(define_insn "sminsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -2359,7 +2365,7 @@ create_template:
"TARGET_PERF_EXT"
"min\t%0, %1, %2"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
(define_insn "*btst"
[(set (match_operand:SI 0 "register_operand" "= r")
@@ -2369,7 +2375,7 @@ create_template:
"TARGET_PERF_EXT"
"btst\t%0, %1, %2"
[(set_attr "type" "alu")
- (set_attr "length" "4")])
+ (set_attr "is_16bit" "no")])
;; ----------------------------------------------------------------------------
