On 11/20/2015 01:23 PM, Richard Henderson wrote: > On 11/20/2015 12:52 PM, Andreas Krebbel wrote: >> +(define_insn "bswaphi2" >> + [(set (match_operand:HI 0 "register_operand" "=d") >> + (bswap:HI (match_operand:HI 1 "memory_operand" "RT")))] >> + "TARGET_CPU_ZARCH" >> + "lrvh\t%0,%1" >> + [(set_attr "type" "load") >> + (set_attr "op_type" "RXY") >> + (set_attr "z10prop" "z10_super")]) > > Surely it's better to arrange so that you can use STRVH as well. > And providing a fallback for the reg-reg case (e.g. LRVR+SRL). > > Although I suppose I don't see support for STRV in bswap32/64 either...
Right, I totally forgot about the stores. I'll have a look. We even have a mem-mem variant (mvcin). But I found it rather difficult to use since the pattern would have to make sure that source and destination do not overlap. -Andreas-
