On Tue, Oct 27, 2015 at 4:45 PM, H.J. Lu <hjl.to...@gmail.com> wrote: > On Tue, Oct 27, 2015 at 1:21 PM, Richard Henderson <r...@redhat.com> wrote: >> The problem in this PR is that a word-mode subreg is used to write to a >> multi-word pseudo, under the assumption that is the correct way to insert a >> value into the appropriate bits of the pseudo. >> >> Except that the pseudo then gets assigned to an SSE register, at which point >> all of the assumptions start to fall apart. Primarily, (subreg X 0) and >> (subreg X 8) do not in the end resolve to different hard registers, so an >> assignment to (subreg X 0) may legitimately clobber all of X. >> >> There *are* ways to insert a value into an element of an SSE register, but >> what >> comes out of reload is indistinguishable from a normal DImode assignment. >> >> An ideal solution would be to use a different method than subregs for >> multi-word registers. Using the same code for "view convert", insert, and >> extract is going to continue to cause us problems. >> >> I had a look over the other major vector targets: >> >> * ppc, sparc, s390 already disallow the described condition. >> >> * arm ought not be subject to this problem because each vector register is >> composed of 4 individually addressable registers. So when (subreg X N) is >> simplified, we really do resolve to the desired hard register. >> >> * aarch64 is almost certainly vulnerable, since it deleted its >> CANNOT_CHANGE_MODE_CLASS implementation in January. I haven't tried to >> create >> a test case that fails for it, but I'm certain it's possible. >> >> >> Tested on x86_64 and committed. >> > > It caused: > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68112
Oops. It should be: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68124 -- H.J.
