James Greenhalgh wrote:
>>
>> - VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
>> + VAR2 (UNOP, vec_unpacks_hi_, 10, v4sf, v8hf)
>
> Should this not use the appropriate "BUILTIN_..." iterator?
Indeed; BUILTIN_VQ_HSF it is.
>> VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
>> VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
I could also use BUILTIN_VQ_HSF here (these two were added in a previous patch,
before the VQ_HSF iterator was introduced). However, that goes against the
principle that we should use the same iterator as the pattern (the pattern uses
the <Vdbl> attribute of the VDF iterator), so I'm not sure whether that would
be preferable (i.e. as a separate patch)?
>> - VAR1 (UNOP, float_extend_lo_, 0, v2df)
>> + VAR2 (UNOP, float_extend_lo_, 0, v2df, v4sf)
>
> Likewise.
Similarly, the required iterator does not exist, as float_extend_lo_ is named
after the <Vwide> attribute of the VDF iterator. The nearest equivalents I can
see use two VAR1's rather than a VAR2, so I've updated the patch to do that too.
OK with those two changes? (patch attached and bootstrapped+check-gcc on
aarch64-none-linux-gnu)
Thanks, Alan
---
gcc/config/aarch64/aarch64-simd-builtins.def | 3 +-
gcc/config/aarch64/aarch64-simd.md | 63 ++++++++++++++++++----------
gcc/config/aarch64/arm_neon.h | 16 +++++--
gcc/config/aarch64/iterators.md | 18 +++++---
4 files changed, 69 insertions(+), 31 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def
b/gcc/config/aarch64/aarch64-simd-builtins.def
index c5b46aa..2c13cfb 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -361,11 +361,12 @@
BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
BUILTIN_VDQF (UNOP, abs, 2)
- VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
+ BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10)
VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
VAR1 (UNOP, float_extend_lo_, 0, v2df)
+ VAR1 (UNOP, float_extend_lo_, 0, v4sf)
BUILTIN_VDF (UNOP, float_truncate_lo_, 0)
/* Implemented by aarch64_ld1<VALL_F16:mode>. */
diff --git a/gcc/config/aarch64/aarch64-simd.md
b/gcc/config/aarch64/aarch64-simd.md
index f8754cd..160acf9 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1691,36 +1691,57 @@
;; Float widening operations.
-(define_insn "vec_unpacks_lo_v4sf"
- [(set (match_operand:V2DF 0 "register_operand" "=w")
- (float_extend:V2DF
- (vec_select:V2SF
- (match_operand:V4SF 1 "register_operand" "w")
- (parallel [(const_int 0) (const_int 1)])
- )))]
+(define_insn "aarch64_simd_vec_unpacks_lo_<mode>"
+ [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+ (float_extend:<VWIDE> (vec_select:<VHALF>
+ (match_operand:VQ_HSF 1 "register_operand" "w")
+ (match_operand:VQ_HSF 2 "vect_par_cnst_lo_half"
"")
+ )))]
"TARGET_SIMD"
- "fcvtl\\t%0.2d, %1.2s"
+ "fcvtl\\t%0.<Vwtype>, %1.<Vhalftype>"
[(set_attr "type" "neon_fp_cvt_widen_s")]
)
-(define_insn "aarch64_float_extend_lo_v2df"
- [(set (match_operand:V2DF 0 "register_operand" "=w")
- (float_extend:V2DF
- (match_operand:V2SF 1 "register_operand" "w")))]
+(define_expand "vec_unpacks_lo_<mode>"
+ [(match_operand:<VWIDE> 0 "register_operand" "")
+ (match_operand:VQ_HSF 1 "register_operand" "")]
"TARGET_SIMD"
- "fcvtl\\t%0.2d, %1.2s"
+ {
+ rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
+ emit_insn (gen_aarch64_simd_vec_unpacks_lo_<mode> (operands[0],
+ operands[1], p));
+ DONE;
+ }
+)
+
+(define_insn "aarch64_simd_vec_unpacks_hi_<mode>"
+ [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+ (float_extend:<VWIDE> (vec_select:<VHALF>
+ (match_operand:VQ_HSF 1 "register_operand" "w")
+ (match_operand:VQ_HSF 2 "vect_par_cnst_hi_half"
"")
+ )))]
+ "TARGET_SIMD"
+ "fcvtl2\\t%0.<Vwtype>, %1.<Vtype>"
[(set_attr "type" "neon_fp_cvt_widen_s")]
)
-(define_insn "vec_unpacks_hi_v4sf"
- [(set (match_operand:V2DF 0 "register_operand" "=w")
- (float_extend:V2DF
- (vec_select:V2SF
- (match_operand:V4SF 1 "register_operand" "w")
- (parallel [(const_int 2) (const_int 3)])
- )))]
+(define_expand "vec_unpacks_hi_<mode>"
+ [(match_operand:<VWIDE> 0 "register_operand" "")
+ (match_operand:VQ_HSF 1 "register_operand" "")]
+ "TARGET_SIMD"
+ {
+ rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
+ emit_insn (gen_aarch64_simd_vec_unpacks_lo_<mode> (operands[0],
+ operands[1], p));
+ DONE;
+ }
+)
+(define_insn "aarch64_float_extend_lo_<Vwide>"
+ [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+ (float_extend:<VWIDE>
+ (match_operand:VDF 1 "register_operand" "w")))]
"TARGET_SIMD"
- "fcvtl2\\t%0.2d, %1.4s"
+ "fcvtl\\t%0<Vmwtype>, %1<Vmtype>"
[(set_attr "type" "neon_fp_cvt_widen_s")]
)
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index c7bfadf..91ada61 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -6025,10 +6025,6 @@ vaddlvq_u32 (uint32x4_t a)
result; \
})
-/* vcvt_f32_f16 not supported */
-
-/* vcvt_high_f32_f16 not supported */
-
#define vcvt_n_f32_s32(a, b) \
__extension__ \
({ \
@@ -13436,6 +13432,12 @@ vcvt_high_f32_f64 (float32x2_t __a, float64x2_t __b)
/* vcvt (float -> double). */
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vcvt_f32_f16 (float16x4_t __a)
+{
+ return __builtin_aarch64_float_extend_lo_v4sf (__a);
+}
+
__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
vcvt_f64_f32 (float32x2_t __a)
{
@@ -13443,6 +13445,12 @@ vcvt_f64_f32 (float32x2_t __a)
return __builtin_aarch64_float_extend_lo_v2df (__a);
}
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vcvt_high_f32_f16 (float16x8_t __a)
+{
+ return __builtin_aarch64_vec_unpacks_hi_v8hf (__a);
+}
+
__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
vcvt_high_f64_f32 (float32x4_t __a)
{
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 3c1c30f..c2af1de 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -91,6 +91,9 @@
;; Vector single Float modes.
(define_mode_iterator VDQSF [V2SF V4SF])
+;; Quad vector Float modes with half/single elements.
+(define_mode_iterator VQ_HSF [V8HF V4SF])
+
;; Modes suitable to use as the return type of a vcond expression.
(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
@@ -492,14 +495,18 @@
(V2SI "V2DI") (V16QI "V8HI")
(V8HI "V4SI") (V4SI "V2DI")
(HI "SI") (SI "DI")
+ (V8HF "V4SF") (V4SF "V2DF")
(V4HF "V4SF") (V2SF "V2DF")]
-
)
-;; Widened mode register suffixes for VD_BHSI/VQW.
+;; Widened modes of vector modes, lowercase
+(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")])
+
+;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
(V2SI "2d") (V16QI "8h")
- (V8HI "4s") (V4SI "2d")])
+ (V8HI "4s") (V4SI "2d")
+ (V8HF "4s") (V4SF "2d")])
;; Widened mode register suffixes for VDW/VQW.
(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
@@ -508,9 +515,10 @@
(V4HF ".4s") (V2SF ".2d")
(SI "") (HI "")])
-;; Lower part register suffixes for VQW.
+;; Lower part register suffixes for VQW/VQ_HSF.
(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
- (V4SI "2s")])
+ (V4SI "2s") (V8HF "4h")
+ (V4SF "2s")])
;; Define corresponding core/FP element mode for each vector mode.
(define_mode_attr vw [(V8QI "w") (V16QI "w")
--
1.8.3
