On Fri, Aug 14, 2015 at 11:46:03AM -0400, Michael Meissner wrote:
> +;; Like int_reg_operand, but don't return true for pseudo registers
> +(define_predicate "int_reg_operand_not_pseudo"
> + (match_operand 0 "register_operand")
> +{
> + if ((TARGET_E500_DOUBLE || TARGET_SPE) && invalid_e500_subreg (op, mode))
> + return 0;
> +
> + if (GET_CODE (op) == SUBREG)
> + op = SUBREG_REG (op);
> +
> + if (!REG_P (op))
> + return 0;
> +
> + if (REGNO (op) >= FIRST_PSEUDO_REGISTER)
> + return 0;
> +
> + return INT_REGNO_P (REGNO (op));
> +})
Since you use this only once, maybe it is easier (to read, etc.) if you
just test it there? Hard regs do not get subregs.
> +(define_insn_and_split "ieee_128bit_vsx_neg<mode>2"
> + [(set (match_operand:TFIFKF 0 "register_operand" "=wa")
> + (neg:TFIFKF (match_operand:TFIFKF 1 "register_operand" "wa")))
> + (clobber (match_scratch:V16QI 2 "=v"))]
> + "TARGET_FLOAT128 && FLOAT128_IEEE_P (<MODE>mode)"
> + "#"
> + "&& 1"
> + [(parallel [(set (match_dup 0)
> + (neg:TFIFKF (match_dup 1)))
> + (use (match_dup 2))])]
> +{
> + if (GET_CODE (operands[2]) == SCRATCH)
> + operands[2] = gen_reg_rtx (V16QImode);
> +
> + operands[3] = gen_reg_rtx (V16QImode);
> + emit_insn (gen_ieee_128bit_negative_zero (operands[2]));
> +}
> + [(set_attr "length" "8")
> + (set_attr "type" "vecsimple")])
Where is operands[3] used? I guess that whole line should be deleted?
> +(define_insn "*ieee_128bit_vsx_neg<mode>2_internal"
> + [(set (match_operand:TFIFKF 0 "register_operand" "=wa")
> + (neg:TFIFKF (match_operand:TFIFKF 1 "register_operand" "wa")))
> + (use (match_operand:V16QI 2 "register_operand" "=v"))]
> + "TARGET_FLOAT128"
> + "xxlxor %x0,%x1,%x2"
> + [(set_attr "length" "4")
> + (set_attr "type" "vecsimple")])
Length 4 is default, you can just leave it out (like we do for most
machine insns already).
Segher
