(-a)*b should not be compiled to vnmul a,b with -frounding-math.
Added a new -(a*b) pattern for vnmul and the old one is only
used if !flag_rounding_math. Updated the costs too.
This is the ARM version of
https://gcc.gnu.org/ml/gcc-patches/2015-07/msg00300.html
Tested with arm-none-linux-gnueabihf cross compiler.
is this OK?
gcc/Changelog:
2015-07-20 Szabolcs Nagy <szabolcs.n...@arm.com>
PR target/66731
* config/arm/arm.md (muldf3negdf_vfp): Handle -frounding-math.
(mulsf3negsf_vfp): Likewise.
* config/arm/arm.c (arm_new_rtx_costs): Fix NEG cost for VNMUL,
fix MULT cost with -frounding-math.
gcc/testsuite/Changelog:
2015-07-20 Szabolcs Nagy <szabolcs.n...@arm.com>
PR target/66731
* gcc.target/arm/vnmul-1.c: New.
* gcc.target/arm/vnmul-2.c: New.
* gcc.target/arm/vnmul-3.c: New.
* gcc.target/arm/vnmul-4.c: New.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 16bda3b..718c759 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -10177,7 +10177,7 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
{
rtx op0 = XEXP (x, 0);
- if (GET_CODE (op0) == NEG)
+ if (GET_CODE (op0) == NEG && !flag_rounding_math)
op0 = XEXP (op0, 0);
if (speed_p)
@@ -10251,6 +10251,13 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
&& (mode == SFmode || !TARGET_VFP_SINGLE))
{
+ if (GET_CODE (XEXP (x, 0)) == MULT)
+ {
+ /* VNMUL. */
+ *cost = rtx_cost (XEXP (x, 0), mode, NEG, 0, speed_p);
+ return true;
+ }
+
if (speed_p)
*cost += extra_cost->fp[mode != SFmode].neg;
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index f62ff79..214c48c 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -770,6 +770,17 @@
[(set (match_operand:SF 0 "s_register_operand" "=t")
(mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
(match_operand:SF 2 "s_register_operand" "t")))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && !flag_rounding_math"
+ "vnmul%?.f32\\t%0, %1, %2"
+ [(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "fmuls")]
+)
+
+(define_insn "*mulsf3negsf_vfp"
+ [(set (match_operand:SF 0 "s_register_operand" "=t")
+ (neg:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
+ (match_operand:SF 2 "s_register_operand" "t"))))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"vnmul%?.f32\\t%0, %1, %2"
[(set_attr "predicable" "yes")
@@ -781,6 +792,18 @@
[(set (match_operand:DF 0 "s_register_operand" "=w")
(mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
(match_operand:DF 2 "s_register_operand" "w")))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE
+ && !flag_rounding_math"
+ "vnmul%?.f64\\t%P0, %P1, %P2"
+ [(set_attr "predicable" "yes")
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "fmuld")]
+)
+
+(define_insn "*muldf3negdf_vfp"
+ [(set (match_operand:DF 0 "s_register_operand" "=w")
+ (neg:DF (mult:DF (match_operand:DF 1 "s_register_operand" "w")
+ (match_operand:DF 2 "s_register_operand" "w"))))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
"vnmul%?.f64\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
diff --git a/gcc/testsuite/gcc.target/arm/vnmul-1.c b/gcc/testsuite/gcc.target/arm/vnmul-1.c
new file mode 100644
index 0000000..0b4ca2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/vnmul-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=hard" } */
+
+double
+foo_d (double a, double b)
+{
+ /* { dg-final { scan-assembler "vnmul\.f64" } } */
+ return -a * b;
+}
+
+float
+foo_s (float a, float b)
+{
+ /* { dg-final { scan-assembler "vnmul\.f32" } } */
+ return -a * b;
+}
diff --git a/gcc/testsuite/gcc.target/arm/vnmul-2.c b/gcc/testsuite/gcc.target/arm/vnmul-2.c
new file mode 100644
index 0000000..f9a8a5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/vnmul-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -frounding-math -mfpu=vfp -mfloat-abi=hard" } */
+
+double
+foo_d (double a, double b)
+{
+ /* { dg-final { scan-assembler "vneg\.f64" } } */
+ /* { dg-final { scan-assembler "vmul\.f64" } } */
+ return -a * b;
+}
+
+float
+foo_s (float a, float b)
+{
+ /* { dg-final { scan-assembler "vneg\.f32" } } */
+ /* { dg-final { scan-assembler "vmul\.f32" } } */
+ return -a * b;
+}
diff --git a/gcc/testsuite/gcc.target/arm/vnmul-3.c b/gcc/testsuite/gcc.target/arm/vnmul-3.c
new file mode 100644
index 0000000..aef99dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/vnmul-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=hard" } */
+
+double
+foo_d (double a, double b)
+{
+ /* { dg-final { scan-assembler "vnmul\.f64" } } */
+ return -(a * b);
+}
+
+float
+foo_s (float a, float b)
+{
+ /* { dg-final { scan-assembler "vnmul\.f32" } } */
+ return -(a * b);
+}
diff --git a/gcc/testsuite/gcc.target/arm/vnmul-4.c b/gcc/testsuite/gcc.target/arm/vnmul-4.c
new file mode 100644
index 0000000..1851c9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/vnmul-4.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -frounding-math -mfpu=vfp -mfloat-abi=hard" } */
+
+double
+foo_d (double a, double b)
+{
+ /* { dg-final { scan-assembler "vnmul\.f64" } } */
+ return -(a * b);
+}
+
+float
+foo_s (float a, float b)
+{
+ /* { dg-final { scan-assembler "vnmul\.f32" } } */
+ return -(a * b);
+}
