On Thu, Jul 16, 2015 at 04:21:15PM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> These are the tests for target attributes and pragmas.
> I've tried to test for the inlining rules, some of the possible errors and
> the preprocessor macros changed from target pragmas.
>
> Ok for trunk?
Mechanical changes in the pragma tests for the sake of grammar!
s/defined but shouldn't/is defined but should not be/
s/not defined but should/is not defined but should be/
Note that some of the errors have different text, so you'll have to run
through by hand and check these are consistent.
It would be good to hand some of these target attribute tests off
to the assembler to make sure we are also putting out appropriate
directives in our output. Perhaps "assemble" is the more appropriate
dg-do directive?
Some more nits below (mostly missing comments on testcases).
Thanks,
James
>
> Thanks,
> Kyrill
>
> 2015-07-16 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
>
> * gcc.target/aarch64/pragma-cpp-predefs-1.c: New test.
> * gcc.target/aarch64/target-attr-1.c: Likewise.
> * gcc.target/aarch64/target-attr-2.c: Likewise.
> * gcc.target/aarch64/target-attr-3.c: Likewise.
> * gcc.target/aarch64/target-attr-4.c: Likewise.
> * gcc.target/aarch64/target-attr-5.c: Likewise.
> * gcc.target/aarch64/target-attr-6.c: Likewise.
> * gcc.target/aarch64/target-attr-7.c: Likewise.
> * gcc.target/aarch64/target-attr-8.c: Likewise.
> * gcc.target/aarch64/target-attr-9.c: Likewise.
> * gcc.target/aarch64/target-attr-10.c: Likewise.
> * gcc.target/aarch64/target-attr-11.c: Likewise.
> * gcc.target/aarch64/target-attr-12.c: Likewise.
> * gcc.target/aarch64/target-attr-13.c: Likewise.
> * gcc.target/aarch64/target-attr-14.c: Likewise.
> commit 1218b6fe4dd6d3429793d62369a878047a9f9a35
> Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
> Date: Thu May 21 15:21:44 2015 +0100
>
> [AArch64][12/N] Target attributes and target pragmas tests
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/pragma-cpp-predefs-1.c
> b/gcc/testsuite/gcc.target/aarch64/pragma-cpp-predefs-1.c
> new file mode 100644
> index 0000000..779220e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/pragma-cpp-predefs-1.c
> @@ -0,0 +1,255 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=armv8-a+crypto" } */
> +
> +/* Test that pragma option pushing and popping works.
Two spaces should be replaced by one.
> +/* And again, but using just the isa extensions. */
s/isa/ISA/
> diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-11.c
> b/gcc/testsuite/gcc.target/aarch64/target-attr-11.c
> new file mode 100644
> index 0000000..f248b35
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/target-attr-11.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +
Comment on what we are testing.
> +__attribute__((target("no-general-regs-only")))
> +int
> +foo (int a)
> +{
> + return a + 1;
> +}
> +
> +/* { dg-error "does not allow a negated form" "" { target *-*-* } 0 } */
> +/* { dg-error "is invalid" "" { target *-*-* } 0 } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-12.c
> b/gcc/testsuite/gcc.target/aarch64/target-attr-12.c
> new file mode 100644
> index 0000000..18af5b3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/target-attr-12.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
Comment on what we are testing.
> diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-13.c
> b/gcc/testsuite/gcc.target/aarch64/target-attr-13.c
> new file mode 100644
> index 0000000..2c9e935
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/target-attr-13.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=armv8-a+crc+crypto" } */
Comment on what we are testing.
> +
> +#include "arm_acle.h"
> +
> +__attribute__((target("+crc+nocrypto")))
> +int
> +foo (uint32_t a, uint8_t b)
> +{
> + return __crc32b (a, b);
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-2.c
> b/gcc/testsuite/gcc.target/aarch64/target-attr-2.c
> new file mode 100644
> index 0000000..a4f32ec
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/target-attr-2.c
> @@ -0,0 +1,36 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -mcpu=cortex-a57 -ftree-vectorize -fdump-tree-vect-all"
> } */
Comment on what we are testing.
> +
> +__attribute__((target("+nosimd")))
> +int
> +baz (int *a)
> +{
> + for (int i = 0; i < 1024; i++)
> + a[i] += 5;
> +}
> +
> +__attribute__((target("arch=armv8-a+nosimd")))
> +int
> +baz2 (int *a)
> +{
> + for (int i = 0; i < 1024; i++)
> + a[i] += 5;
> +}
> +
> +__attribute__((target("cpu=cortex-a53+nosimd")))
> +int
> +baz3 (int *a)
> +{
> + for (int i = 0; i < 1024; i++)
> + a[i] += 5;
> +}
> +
> +__attribute__((target("general-regs-only")))
> +int
> +baz4 (int *a)
> +{
> + for (int i = 0; i < 1024; i++)
> + a[i] += 5;
> +}
> +
> +/* { dg-final { scan-tree-dump-not "vectorized 1 loops" "vect" } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-4.c
> b/gcc/testsuite/gcc.target/aarch64/target-attr-4.c
> new file mode 100644
> index 0000000..f2d9bc1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/target-attr-4.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=armv8-a+nocrc -save-temps" } */
Comment on what we are testing.
> +
> +#include "arm_acle.h"
> +
> +__attribute__((target("+crc")))
> +uint32_t
> +foo (uint32_t a, uint8_t b)
> +{
> + return __crc32b (a, b);
> +}
> +
> +__attribute__((target("arch=armv8-a+crc")))
> +uint32_t
> +fooarch (uint32_t a, uint8_t b)
> +{
> + return __crc32b (a, b);
> +}
> +
> +__attribute__((target("cpu=cortex-a53+crc")))
> +uint32_t
> +foocpu (uint32_t a, uint8_t b)
> +{
> + return __crc32b (a, b);
> +}
> +
Extra newline.
> +
> +/* { dg-final { scan-assembler-times "crc32b\tw..?, w..?, w..?\n" 3 } } */
