After Kyrill's patch (r225996) (changing combine to do simplification
before doing some transformations) a shortcoming of the rs6000 backend
becomes obvious: we have no patterns to handle
(set (reg:DI) (lt:DI (reg:SI) (const_int 0)))
although we can do that with a single rotate-and-mask instruction.
Previously, combine usually came up with a more complex pattern (that
we do implement), hiding the issue.
This patch adds a define_insn for the pattern.
2015-07-20 Segher Boessenkool <seg...@kernel.crashing.org>
* config/rs6000/rs6000.md (*lt0_disi): New.
---
gcc/config/rs6000/rs6000.md | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5727068..55ceb66 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3475,6 +3475,17 @@ (define_insn_and_split "*rotl<mode>3_mask_dot2"
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
+; Special case for less-than-0. We can do it with just one machine
+; instruction, but the generic optimizers do not realise it is cheap.
+(define_insn "*lt0_disi"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (lt:DI (match_operand:SI 1 "gpc_reg_operand" "r")
+ (const_int 0)))]
+ "TARGET_POWERPC64"
+ "rlwinm %0,%1,1,31,31"
+ [(set_attr "type" "shift")])
+
+
; Two forms for insert (the two arms of the IOR are not canonicalized,
; both are an AND so are the same precedence).
--
1.8.1.4
