On Sun, Jul 12, 2015 at 10:56 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
> On Sat, Jul 11, 2015 at 9:23 PM, H.J. Lu <hjl.to...@gmail.com> wrote:
>> On Thu, Jul 09, 2015 at 01:58:22PM -0700, H.J. Lu wrote:
>>> On Thu, Jul 09, 2015 at 12:13:38PM -0700, H.J. Lu wrote:
>>> > ix86_split_long_move can optimize floating point constant move, which
>>> > can be used to optimize SFmode move for IA MCU.
>>> >
>>> > OK for trunk if there is no regression?
>>> >
>>> >
>>> > H.J.
>>> > ---
>>> > gcc/
>>> >
>>> > PR target/66824
>>> > * config/i386/i386.c (ix86_split_to_parts): Allow SFmode move
>>> > for IA MCU.
>>> > (ix86_split_long_move): Support single move.
>>> > * config/i386/i386.md (FP splitter): Allow SFmode for IA MCU.
>>> >
>>> > gcc/testsuite/
>>> >
>>> > PR target/66824
>>> > * gcc.target/i386/pr66824.c: New test.
>>> > ---
>>>
>>>
>>> I missed the testcase. Here is the updated patch.
>>>
>>
>> ix86_split_long_move can optimize floating point constant move, which
>> can be used to optimize SFmode move with software floating point.
>>
>> OK for trunk if there are no regressions?
>
> No, this patch is wrong. Please investigate why "*movsf_internal"
> doesn't use "?r/rmF" alternative in case FP regs are unavailable.
> Perhaps you should add new alternative with a conditional constraint,
> but without "?". And... please use:
>
I couldn't figure a way to add conditional constraints for "?r/rmF" and
"r/rmF". I simply disabled *movsf_internal if TARGET_HARD_FP_REGS
is false and added a new "*movsf_internal_soft_fp" pattern.
OK for trunk if there is no regressions?
> #define TARGET_HARD_FP_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE)
>
> Uros.
Thanks.
--
H.J.
From 87a92b1168c37e7607d0c839860f2eecf0f34345 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.to...@gmail.com>
Date: Thu, 9 Jul 2015 12:06:40 -0700
Subject: [PATCH] Add *movsf_internal_soft_fp pattern
Without hard floating point registers, general purpose registers are
used and we should generate mov with general purpose registers for
SFmode load/store.
gcc/
PR target/66824
* config/i386/i386.h (TARGET_HARD_FP_REGS): New.
* config/i386/i386.md (*movsf_internal): Enable only if
TARGET_HARD_FP_REGS is true.
(*movsf_internal_soft_fp): New pattern. Enable only if
TARGET_HARD_FP_REGS is false.
gcc/testsuite/
PR target/66824
* gcc.target/i386/pr66824.c: New test.
Revert ix86_split_to_parts/FP splitter
pr66824
---
gcc/config/i386/i386.h | 2 ++
gcc/config/i386/i386.md | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/pr66824.c | 29 +++++++++++++++++++++++++++++
3 files changed, 43 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/pr66824.c
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 0fcf391..3b7cf92 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -164,6 +164,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define TARGET_16BIT TARGET_CODE16
#define TARGET_16BIT_P(x) TARGET_CODE16_P(x)
+#define TARGET_HARD_FP_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE)
+
/* SSE4.1 defines round instructions */
#define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1
#define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 354532a..c83cf6d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3325,6 +3325,7 @@
(match_operand:SF 1 "general_operand"
"Yf*fm,Yf*f,G ,rmF,rF,C,v,m,v,Yj,r ,*y ,m ,*y,*Yn,r"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
+ && TARGET_HARD_FP_REGS
&& (!can_create_pseudo_p ()
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
|| !CONST_DOUBLE_P (operands[1])
@@ -3444,6 +3445,17 @@
]
(const_string "SF")))])
+(define_insn "*movsf_internal_soft_fp"
+ [(set (match_operand:SF 0 "nonimmediate_operand"
+ "=r ,m")
+ (match_operand:SF 1 "general_operand"
+ "rmF,rF"))]
+ "!(MEM_P (operands[0]) && MEM_P (operands[1]))
+ && !TARGET_HARD_FP_REGS"
+ "mov{l}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "imov")
+ (set_attr "mode" "SI")])
+
(define_split
[(set (match_operand 0 "any_fp_register_operand")
(match_operand 1 "memory_operand"))]
diff --git a/gcc/testsuite/gcc.target/i386/pr66824.c b/gcc/testsuite/gcc.target/i386/pr66824.c
new file mode 100644
index 0000000..3511e4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr66824.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-O2 -mno-sse -mno-mmx -mno-80387" } */
+/* { dg-final { scan-assembler-not "\.LC\[0-9\]" } } */
+
+double foo (float);
+
+double
+f1 (void)
+{
+ return foo (1.0);
+}
+
+double
+f2 (void)
+{
+ return foo (0.0);
+}
+
+void
+f3 (float *x, float t)
+{
+ *x = 0.0 + t;
+}
+
+float
+f4 (void)
+{
+ return 1.0;
+}
--
2.4.3
