[PATCH 3/3][AArch64 nofp] Fix another ICE with +nofp/-mgeneral-regs-only

[Alan Lawrence]

This fixes another ICE, obtained with the attached testcase - yes, there was a 
way to get hold of a float, without passing an argument or going through 
movsf/movdf!

Bootstrapped + check-gcc on aarch64-none-linux-gnu.
gcc/ChangeLog:

        * config/aarch64/aarch64.md (<optab><fcvt_target><GPF:mode>2):
        Condition on TARGET_FLOAT.

gcc/testsuite/ChangeLog:

        * gcc.target/aarch64/mgeneral-regs_3.c: New.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 99cefece8093791ccf17cb071a4e9997bda8fd89..bcaafda5ea46f136dc90f34aa8f2dfaddabd09f5 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4106,7 +4106,7 @@
 (define_insn "<optab><fcvt_target><GPF:mode>2"
   [(set (match_operand:GPF 0 "register_operand" "=w,w")
         (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand" "w,r")))]
-  ""
+  "TARGET_FLOAT"
   "@
    <su_optab>cvtf\t%<GPF:s>0, %<s>1
    <su_optab>cvtf\t%<GPF:s>0, %<w1>1"
diff --git a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..225d9eaa45530d88315a146f3fae72d86fe66373
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_3.c
@@ -0,0 +1,11 @@
+/* { dg-options "-mgeneral-regs-only -O2" } */
+
+extern void abort (void);
+
+int
+test (int i, ...)
+{
+  float f = (float) i; /* { dg-error "'-mgeneral-regs-only' is incompatible with floating point code" } */
+  if (f != f) abort ();
+  return 2;
+}