On Wed, Jul 20, 2011 at 9:06 PM, H.J. Lu <hongjiu...@intel.com> wrote:
> The testcase is gcc.c-torture/compile/pr45728.c. This patch zero-extends
> symbol address to 64bit if needd. OK for trunk?
>
> Thanks.
>
>
> H.J.
> ----
> 2011-07-20 H.J. Lu <hongjiu...@intel.com>
>
> PR target/49798
> * config/i386/i386.c (ix86_asm_integer): New.
> (TARGET_ASM_INTEGER): Likewise.
>
This is the updated patch, using the same approach in sparc_assemble_integer.
OK for trunk?
Thanks.
H.J.
2011-07-21 H.J. Lu <hongjiu...@intel.com>
PR target/49798
* config/i386/i386.c (ix86_asm_integer): New.
(TARGET_ASM_INTEGER): Likewise.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index a60085c..d72edff 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -14289,6 +14289,24 @@ i386_asm_output_addr_const_extra (FILE *file, rtx x)
return true;
}
+
+/* Implementation of TARGET_ASM_INTEGER. */
+
+static bool
+ix86_asm_integer (rtx x, unsigned int size, int aligned_p)
+{
+ if (TARGET_X32
+ && size == 8
+ && !CONST_INT_P (x)
+ && !CONST_DOUBLE_P (x))
+ {
+ /* Zero-extend symbol address to 64bit. */
+ default_assemble_integer (x, 4, aligned_p);
+ default_assemble_integer (const0_rtx, 4, aligned_p);
+ return true;
+ }
+ return default_assemble_integer (x, size, aligned_p);
+}
/* Split one or more double-mode RTL references into pairs of half-mode
references. The RTL can be REG, offsettable MEM, integer constant, or
@@ -34892,6 +34910,8 @@ ix86_autovectorize_vector_sizes (void)
#define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
#undef TARGET_ASM_UNALIGNED_DI_OP
#define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
+#undef TARGET_ASM_INTEGER
+#define TARGET_ASM_INTEGER ix86_asm_integer
#undef TARGET_PRINT_OPERAND
#define TARGET_PRINT_OPERAND ix86_print_operand
