[Patch MIPS] Enable TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS hook

[Robert Suchanek]

Hi,

The patch enables the hook for MIPS as a result of the discussion:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65862

Tested on mips-mti-linux-gnu and mips-img-linux-gnu. Ok to apply?

Regards,
Robert

gcc/ChangeLog:

        * config/mips/mips.c (mips_ira_change_pseudo_allocno_class): New
        function.
        (TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS): Define macro.

gcc/testsuite/ChangeLog:

        * gcc.target/mips/pr65862-1.c: New test.
        * gcc.target/mips/pr65862-2.c: Likewise.
---
 gcc/config/mips/mips.c                    | 13 +++++++++++++
 gcc/testsuite/gcc.target/mips/pr65862-1.c | 16 ++++++++++++++++
 gcc/testsuite/gcc.target/mips/pr65862-2.c | 31 +++++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/pr65862-1.c
 create mode 100644 gcc/testsuite/gcc.target/mips/pr65862-2.c

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index c3755f5..3c8ac30 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -19415,6 +19415,17 @@ mips_lra_p (void)
 {
   return mips_lra_flag;
 }
+
+/* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.  */
+
+static reg_class_t
+mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class)
+{
+  if (FLOAT_MODE_P (PSEUDO_REGNO_MODE (regno)) || allocno_class != ALL_REGS)
+    return allocno_class;
+  return GR_REGS;
+}
+
 

 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
@@ -19671,6 +19682,8 @@ mips_lra_p (void)
 #define TARGET_SPILL_CLASS mips_spill_class
 #undef TARGET_LRA_P
 #define TARGET_LRA_P mips_lra_p
+#undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
+#define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS 
mips_ira_change_pseudo_allocno_class
 
 struct gcc_target targetm = TARGET_INITIALIZER;
 

diff --git a/gcc/testsuite/gcc.target/mips/pr65862-1.c 
b/gcc/testsuite/gcc.target/mips/pr65862-1.c
new file mode 100644
index 0000000..0c00092
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/pr65862-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\\\$f\[0-9\]+" } } */
+int a, c;
+int *b, *d;
+void
+fn1(int p1, int *p2(void *, void *), void *p3(void *, void *, int)) {
+  int n = c;
+  for (;;) {
+    a = 1;
+    for (; a < n;) {
+      *d = p1 && p2(0, (int *) ((long)p1 + 1));
+      p3(0, b + p1, 0);
+    }
+  }
+}
diff --git a/gcc/testsuite/gcc.target/mips/pr65862-2.c 
b/gcc/testsuite/gcc.target/mips/pr65862-2.c
new file mode 100644
index 0000000..c6a2641
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/pr65862-2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\\\$f\[0-9\]+" } } */
+int a, b, d, e, j, k, n, o;
+unsigned c, h, i, l, m, p;
+int *f;
+int *g;
+int fn1(int p1) { return p1 - a; }
+
+int fn2() {
+  b = b + 1 - a;
+  e = 1 + o + 1518500249;
+  d = d + n;
+  c = (int)c + g[0];
+  b = b + m + 1;
+  d = d + p + 1518500249;
+  d = d + k - 1;
+  c = fn1(c + j + 1518500249);
+  e = fn1(e + i + 1);
+  d = d + h + 1859775393 - a;
+  c = fn1(c + (d ^ 1 ^ b) + g[1] + 1);
+  b = fn1(b + m + 3);
+  d = fn1(d + l + 1);
+  b = b + (c ^ 1) + p + 1;
+  e = fn1(e + (b ^ c ^ d) + n + 1);
+  d = o;
+  b = 0;
+  e = e + k + 1859775393;
+  f[0] = e;
+  return a;
+}
-- 
2.2.2