All,
This patch removes the special casing for targets with relaxed memory
ordering and handles guard accesses with equivalent atomic load acquire
operations. In this process we change the algorithm to load the guard
variable with an atomic load that has ACQUIRE semantics. I'm not
terribly familiar with the C++ front-end so I'm not sure I've used the
appropriate interfaces for doing something like this.
This then means that on targets which have weak memory models, the fast
path is inlined and can directly use a load-acquire instruction where
available (and yay! one more hook gone).
Currently bootstrapping and regression testing on AArch64 and ARM (prior
to the commit that caused PR66241). If this goes in then I'm happy to
withdraw part of the patches to trunk for AArch64 / ARM that defines
TARGET_RELAXED_ORDERING and only propose those hunks to the branches.
I'd also request the other target maintainers CC'd to help by testing
this on their platforms as I do not have access to all of them.
To help folks see the difference, this is the difference in output for a
compiler for AArch64 built with TARGET_RELAXED_ORDERING set to true and
this patch for the testcase below.
int* f(void) {
static int* p = new int;
return p;
}
- adrp x19, .LANCHOR0
- add x20, x19, :lo12:.LANCHOR0
- mov x0, x20
- bl __cxa_guard_acquire
- cbnz w0, .L2
- ldr x0, [x20, 8]
+ adrp x20, .LANCHOR0
+ add x19, x20, :lo12:.LANCHOR0
+ ldar x0, [x19]
+ tbz x0, 0, .L11
+.L9:
+ ldr x0, [x19, 8]
regards
Ramana
2015-05-22 Ramana Radhakrishnan <ramana.radhakrish...@arm.com>
PR c++/66192
* config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Likewise.
* config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Likewise.
* config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Likewise.
* config/sparc/linux.h (SPARC_RELAXED_ORDERING): Likewise.
* config/sparc/linux64.h (SPARC_RELAXED_ORDERING): Likewise.
* config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Likewise.
* config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Likewise.
* doc/tm.texi: Regenerate.
* doc/tm.texi.in (TARGET_RELAXED_ORDERING): Delete.
* target.def (TARGET_RELAXED_ORDERING): Delete.
gcc/cp/ChangeLog:
2015-05-22 Ramana Radhakrishnan <ramana.radhakrish...@arm.com>
PR c++/66192
* decl.c (expand_static_init): Remove special casing for
targets with weak memory model.
* decl2.c (build_atomic_load): New function.
(get_guard_cond): Adjust for atomic_load.
