> Hi,
>
> Looks like I missed some splits, which caused PR65915.
> Patch below fixes it.
> Ok for trunk?
>
> 2015-04-28 Ilya Tocar <ilya.to...@intel.com>
>
> * config/i386/i386.md (define_split): Check for xmm16+,
> when splitting scalar float conversion.
>
>
> ---
> gcc/config/i386/i386.md | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index 937871a..af1cd9b 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -4897,7 +4897,9 @@
> "TARGET_SSE2 && TARGET_SSE_MATH
> && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
> && reload_completed && SSE_REG_P (operands[0])
> - && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)"
> + && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)
> + && (!EXT_REX_SSE_REG_P (operands[0])
> + || TARGET_AVX512VL)"
> [(const_int 0)]
> {
> operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
> @@ -4921,7 +4923,9 @@
> "TARGET_SSE2 && TARGET_SSE_MATH
> && TARGET_SSE_PARTIAL_REG_DEPENDENCY
> && optimize_function_for_speed_p (cfun)
> - && reload_completed && SSE_REG_P (operands[0])"
> + && reload_completed && SSE_REG_P (operands[0])
> + && (!EXT_REX_SSE_REG_P (operands[0])
> + || TARGET_AVX512VL)"
> [(const_int 0)]
> {
> const machine_mode vmode = <MODEF:ssevecmode>mode;
> --
> 1.8.3.1
>
Updated version below (now with test).
---
gcc/config/i386/i386.md | 8 ++++++--
gcc/config/i386/sse.md | 6 +++---
gcc/testsuite/gcc.target/i386/pr65915.c | 6 ++++++
3 files changed, 15 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr65915.c
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 937871a..af1cd9b 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4897,7 +4897,9 @@
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed && SSE_REG_P (operands[0])
- && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)"
+ && (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)
+ && (!EXT_REX_SSE_REG_P (operands[0])
+ || TARGET_AVX512VL)"
[(const_int 0)]
{
operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0],
@@ -4921,7 +4923,9 @@
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_SSE_PARTIAL_REG_DEPENDENCY
&& optimize_function_for_speed_p (cfun)
- && reload_completed && SSE_REG_P (operands[0])"
+ && reload_completed && SSE_REG_P (operands[0])
+ && (!EXT_REX_SSE_REG_P (operands[0])
+ || TARGET_AVX512VL)"
[(const_int 0)]
{
const machine_mode vmode = <MODEF:ssevecmode>mode;
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 9b7009a..c61098d 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -4258,11 +4258,11 @@
(set_attr "mode" "TI")])
(define_insn "sse2_cvtsi2sd"
- [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
(vec_merge:V2DF
(vec_duplicate:V2DF
(float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m,rm")))
- (match_operand:V2DF 1 "register_operand" "0,0,x")
+ (match_operand:V2DF 1 "register_operand" "0,0,v")
(const_int 1)))]
"TARGET_SSE2"
"@
@@ -4275,7 +4275,7 @@
(set_attr "amdfam10_decode" "vector,double,*")
(set_attr "bdver1_decode" "double,direct,*")
(set_attr "btver2_decode" "double,double,double")
- (set_attr "prefix" "orig,orig,vex")
+ (set_attr "prefix" "orig,orig,maybe_evex")
(set_attr "mode" "DF")])
(define_insn "sse2_cvtsi2sdq<round_name>"
diff --git a/gcc/testsuite/gcc.target/i386/pr65915.c
b/gcc/testsuite/gcc.target/i386/pr65915.c
new file mode 100644
index 0000000..990c5aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr65915.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -fpic -mcmodel=medium" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target lp64 } */
+
+#include "avx512f-vrndscalepd-2.c"
--
1.8.3.1
