On Wed, Apr 29, 2015 at 9:02 PM, Uros Bizjak <ubiz...@gmail.com> wrote:
> Hello!
>
> Attached patch implements a CCZ-only setting pattern for a couple of
> BMI[,2] intrinsics.
These two insns are three operand instructions, and some peephole2
patterns were not prepared for this. Please note that clobbered
register can be different than input registers. Attached patch fixes
this omission.
2015-04-29 Uros Bizjak <ubiz...@gmail.com>
PR target/65871
* config/i386/i386.md (*bmi_bextr_<mode>_cczonly): New pattern.
(*bmi2_bzhi_<mode>3_1_cczonly): Ditto.
(setcc+movzbl peephole2): Check also clobbered reg.
(setcc+andl peephole2): Ditto.
Tested on x86_64-linux-gnu {,-m32} and committed to mainline SVN.
Uros.
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 222590)
+++ config/i386/i386.md (working copy)
@@ -11567,7 +11567,9 @@
(zero_extend (match_dup 1)))]
"(peep2_reg_dead_p (3, operands[1])
|| operands_match_p (operands[1], operands[3]))
- && ! reg_overlap_mentioned_p (operands[3], operands[0])"
+ && ! reg_overlap_mentioned_p (operands[3], operands[0])
+ && ! (GET_CODE (operands[4]) == CLOBBER
+ && reg_mentioned_p (operands[3], operands[4]))"
[(parallel [(set (match_dup 5) (match_dup 0))
(match_dup 4)])
(set (strict_low_part (match_dup 6))
@@ -11610,7 +11612,9 @@
(clobber (reg:CC FLAGS_REG))])]
"(peep2_reg_dead_p (3, operands[1])
|| operands_match_p (operands[1], operands[3]))
- && ! reg_overlap_mentioned_p (operands[3], operands[0])"
+ && ! reg_overlap_mentioned_p (operands[3], operands[0])
+ && ! (GET_CODE (operands[4]) == CLOBBER
+ && reg_mentioned_p (operands[3], operands[4]))"
[(parallel [(set (match_dup 5) (match_dup 0))
(match_dup 4)])
(set (strict_low_part (match_dup 6))
