On Wed, Apr 22, 2015 at 06:08:26PM -0500, Peter Bergner wrote: > > > > > + case HTM_BUILTIN_TTEST: /* Alias for: tabortwci. 0,r0,0 */ > > > > > + op[nopnds++] = GEN_INT (0); > > > > > + op[nopnds++] = gen_rtx_REG (SImode, 0); > > > > > + op[nopnds++] = GEN_INT (0); > > > > > > > > Is that really r0, isn't that (0|rA)? [Too lazy to read the docs myself > > > > right now, sorry.] > > > > > > The ISA doc shows: > > > > [snip] > > > > Thanks for looking it up! > > > > I'm still a bit worried about putting a reg in the RTL (while the > > instruction > > doesn't actually use one), but perhaps it's harmless. > > I'm not sure what you mean by the "instruction doesn't use one". > The hardware instruction does use a register for its second > operand (even though its contents are ignored due to TO == 0) > and the pattern requires us to pass in a reg rtx, so I'm not > sure what you're referring to.
I mean the instruction doesn't actually use the value in the register (if it did, you couldn't just pass in a non-fixed hard register in RTL). Using a hard reg in the RTL like this has a few problems: a) It might hinder register allocation. Maybe it doesn't, not sure; b) It does hinder scheduling; c) It can make things ICE, maybe with register asm. I no longer think c) will happen in this case. The alternative is to write a separate define_insn for ttest, one without inputs; the generated assembler can still be the same of course. Cheers, Segher
