Hi,
I am checking the following patches to revert 32bit address changes in
x32 mode.
H.J.
commit 2087dd1362a4c2095a03ea92a06a9b67ab516a02
Author: H.J. Lu <hjl.to...@gmail.com>
Date: Sun Jul 17 16:16:16 2011 -0700
Remove ix86_simplify_base_index_disp.
diff --git a/gcc/ChangeLog.addr32 b/gcc/ChangeLog.addr32
new file mode 100644
index 0000000..2cf6b3f
--- /dev/null
+++ b/gcc/ChangeLog.addr32
@@ -0,0 +1,10 @@
+2011-07-17 Uros Bizjak <ubiz...@gmail.com>
+
+ PR target/47744
+ * config/i386/i386.c (ix86_decompose_address): Properly handle
+ SUBREG for x32.
+
+2011-07-17 H.J. Lu <hongjiu...@intel.com>
+
+ * config/i386/i386.c (ix86_simplify_base_index_disp): Removed.
+ (ix86_decompose_address): Don't call it.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index c728c51..c8989ed 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -11100,190 +11100,6 @@ ix86_live_on_entry (bitmap regs)
}
}
-/* For TARGET_X32, IRA may generate
-
- (set (reg:SI 40 r11)
- (plus:SI (plus:SI (mult:SI (reg:SI 1 dx)
- (const_int 8))
- (subreg:SI (plus:DI (reg/f:DI 7 sp)
- (const_int CONST1)) 0))
- (const_int CONST2)))
-
- We translate it into
-
- (set (reg:SI 40 r11)
- (plus:SI (plus:SI (mult:SI (reg:SI 1 dx)
- (const_int 8))
- (reg/f:SI 7 sp))
- (const_int [CONST1 + CONST2])))
-
- We also translate
-
- (plus:DI (zero_extend:DI (plus:SI (plus:SI (reg:SI 4 si [70])
- (reg:SI 2 cx [86]))
- (const_int CONST1)))
- (const_int CONST2))
-
- into
-
- (plus:DI (zero_extend:DI (plus:SI (reg:SI 4 si [70])
- (reg:SI 2 cx [86]))
- (const_int [CONST1 + CONST2])))
-
- We also translate
-
- (plus:SI (plus:SI (plus:SI (reg:SI 4 si [70])
- (reg:SI 2 cx [86]))
- (symbol_ref:SI ("A.193.2210")))
- (const_int CONST))
-
- into
-
- (plus:SI (plus:SI (reg:SI 4 si [70])
- (reg:SI 2 cx [86]))
- (const (plus:SI (symbol_ref:SI ("A.193.2210"))
- (const_int CONST))))
-
- We also translate
-
- (plus:SI (reg:SI 0 ax [orig:74 D.4067 ] [74])
- (subreg:SI (plus:DI (reg/f:DI 7 sp)
- (const_int 64 [0x40])) 0))
-
- into
-
- (plus:SI (reg:SI 0 ax [orig:74 D.4067 ] [74])
- (plus:SI (reg/f:SI 7 sp) (const_int 64 [0x40])))
-
- If PLUS is true, we also translate
-
- (set (reg:SI 40 r11)
- (plus:SI (plus:SI (reg:SI 1 dx)
- (subreg:SI (plus:DI (reg/f:DI 7 sp)
- (const_int CONST1)) 0))
- (const_int CONST2)))
-
- into
-
- (set (reg:SI 40 r11)
- (plus:SI (plus:SI (reg:SI 1 dx)
- (reg/f:SI 7 sp))
- (const_int [CONST1 + CONST2])))
-
- */
-
-static void
-ix86_simplify_base_index_disp (rtx *base_p, rtx *index_p, rtx *disp_p,
- bool plus)
-{
- rtx base = *base_p;
- rtx disp, index, op0, op1;
-
- if (!base || GET_MODE (base) != ptr_mode)
- return;
-
- disp = *disp_p;
- if (disp != NULL_RTX
- && disp != const0_rtx
- && !CONST_INT_P (disp))
- return;
-
- if (GET_CODE (base) == SUBREG)
- base = SUBREG_REG (base);
-
- if (GET_CODE (base) == PLUS)
- {
- rtx addend;
-
- op0 = XEXP (base, 0);
- op1 = XEXP (base, 1);
-
- if ((REG_P (op0)
- || (!plus
- && GET_CODE (op0) == PLUS
- && GET_MODE (op0) == ptr_mode
- && REG_P (XEXP (op0, 0))
- && REG_P (XEXP (op0, 1))))
- && (CONST_INT_P (op1)
- || GET_CODE (op1) == SYMBOL_REF
- || GET_CODE (op1) == LABEL_REF))
- {
- base = op0;
- addend = op1;
- }
- else if (REG_P (op1)
- && (CONST_INT_P (op0)
- || GET_CODE (op0) == SYMBOL_REF
- || GET_CODE (op0) == LABEL_REF))
- {
- base = op1;
- addend = op0;
- }
- else if (plus
- && GET_CODE (op1) == SUBREG
- && GET_MODE (op1) == ptr_mode)
- {
- op1 = SUBREG_REG (op1);
- if (GET_CODE (op1) == PLUS)
- {
- addend = XEXP (op1, 1);
- op1 = XEXP (op1, 0);
- if (REG_P (op1) && CONST_INT_P (addend))
- {
- op1 = gen_rtx_REG (ptr_mode, REGNO (op1));
- *base_p = gen_rtx_PLUS (ptr_mode, op0, op1);
- }
- else
- return;
- }
- else
- return;
- }
- else
- return;
-
- if (disp == NULL_RTX || disp == const0_rtx)
- *disp_p = addend;
- else
- {
- if (CONST_INT_P (addend))
- *disp_p = GEN_INT (INTVAL (disp) + INTVAL (addend));
- else
- {
- disp = gen_rtx_PLUS (ptr_mode, addend, disp);
- *disp_p = gen_rtx_CONST (ptr_mode, disp);
- }
- }
-
- if (!plus)
- {
- if (REG_P (base))
- *base_p = gen_rtx_REG (ptr_mode, REGNO (base));
- else
- *base_p = base;
- }
- }
- else if (!plus
- && (disp == NULL_RTX || disp == const0_rtx)
- && index_p
- && (index = *index_p) != NULL_RTX
- && GET_CODE (index) == SUBREG
- && GET_MODE (index) == ptr_mode)
- {
- index = SUBREG_REG (index);
- if (GET_CODE (index) == PLUS && GET_MODE (index) == Pmode)
- {
- op0 = XEXP (index, 0);
- op1 = XEXP (index, 1);
- if (REG_P (op0) && CONST_INT_P (op1))
- {
- *index_p = gen_rtx_REG (ptr_mode, REGNO (op0));
- *disp_p = op1;
- }
- }
- }
-}
-
/* Extract the parts of an RTL expression that is a valid memory address
for an instruction. Return 0 if the structure of the address is
grossly off. Return -1 if the address contains ASHIFT, so it is not
@@ -11321,24 +11137,6 @@ ix86_decompose_address (rtx addr, struct ix86_address
*out)
return 0;
addends[n++] = XEXP (op, 1);
op = XEXP (op, 0);
- /* Support 32bit address in x32 mode. */
- if (TARGET_X32 && reload_completed)
- {
- if (GET_CODE (op) == ZERO_EXTEND
- && GET_MODE (op) == Pmode
- && GET_CODE (XEXP (op, 0)) == PLUS)
- {
- op = XEXP (op, 0);
- if (n == 1)
- ix86_simplify_base_index_disp (&op, NULL,
- &addends[0], false);
- }
- else if (n == 1
- && GET_CODE (op) == PLUS
- && GET_MODE (op) == ptr_mode)
- ix86_simplify_base_index_disp (&op, NULL, &addends[0],
- true);
- }
}
while (GET_CODE (op) == PLUS);
if (n >= 4)
@@ -11379,8 +11177,12 @@ ix86_decompose_address (rtx addr, struct ix86_address
*out)
return 0;
break;
- case REG:
case SUBREG:
+ if (TARGET_X32
+ && !register_no_elim_operand (op, Pmode))
+ return 0;
+
+ case REG:
if (!base)
base = op;
else if (!index)
@@ -11432,9 +11234,6 @@ ix86_decompose_address (rtx addr, struct ix86_address
*out)
scale = INTVAL (scale_rtx);
}
- if (TARGET_X32 && reload_completed)
- ix86_simplify_base_index_disp (&base, &index, &disp, false);
-
/* Avoid useless 0 displacement. */
if (disp == const0_rtx && (base || index))
disp = NULL_RTX;
commit 211cfc28a9941a033fc23af41bbd9310d001cedf
Author: H.J. Lu <hjl.to...@gmail.com>
Date: Sun Jul 17 16:17:25 2011 -0700
Remove x32 specific LEA patterns.
diff --git a/gcc/ChangeLog.addr32 b/gcc/ChangeLog.addr32
index 2cf6b3f..fcfaf25 100644
--- a/gcc/ChangeLog.addr32
+++ b/gcc/ChangeLog.addr32
@@ -1,3 +1,10 @@
+2011-07-17 H.J. Lu <hongjiu...@intel.com>
+
+ * config/i386/i386.md (*lea_0_x32): Removed.
+ (*lea_2_x32): Likewise.
+ (*lea_2_zext_x32): Likewise.
+ (X32 LEA zero-extend split): Likewise.
+
2011-07-17 Uros Bizjak <ubiz...@gmail.com>
PR target/47744
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2f2e491..36cdec1 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5443,34 +5443,6 @@
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
-;; Used by reload to support addresses with complex expressions.
-(define_insn_and_split "*lea_0_x32"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (plus:SI
- (subreg:SI
- (plus:DI
- (match_operand:DI 1 "pointer_register_operand" "r")
- (match_operand:DI 2 "immediate_operand" "n")) 0)
- (match_operand:SI 3 "immediate_operand" "n")))]
- "TARGET_X32 && !can_create_pseudo_p ()"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- rtx pat, src, insn;
- pat = gen_rtx_PLUS (DImode, operands[1], operands[2]);
- src = gen_rtx_PLUS (SImode, gen_rtx_SUBREG (SImode, pat, 0),
- operands[3]);
- operands[1] = gen_lowpart (SImode, operands[1]);
- operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
- pat = gen_rtx_PLUS (SImode, operands[1], operands[2]);
- insn = emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
- set_unique_reg_note (insn, REG_EQUIV, src);
- DONE;
-}
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
(define_insn "*lea_1"
[(set (match_operand:P 0 "register_operand" "=r")
(match_operand:P 1 "no_seg_address_operand" "p"))]
@@ -5487,16 +5459,6 @@
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
-;; Place this after lea_2 since 64bit version doesn't have address
-;; size override.
-(define_insn "*lea_2_x32"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "no_seg_address_operand" "p"))]
- "TARGET_X32"
- "lea{l}\t{%a1, %0|%0, %a1}"
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
(define_insn "*lea_2_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
@@ -5506,15 +5468,6 @@
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
-(define_insn "*lea_2_zext_x32"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI
- (match_operand:SI 1 "no_seg_address_operand" "p")))]
- "TARGET_X32"
- "lea{l}\t{%a1, %k0|%k0, %a1}"
- [(set_attr "type" "lea")
- (set_attr "mode" "SI")])
-
(define_insn "*add<mode>_1"
[(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r")
(plus:SWI48
@@ -5921,19 +5874,6 @@
operands[2] = gen_lowpart (DImode, operands[2]);
})
-;; Convert lea to the lea pattern to avoid flags dependency.
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI
- (plus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" ""))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_X32
- && reload_completed
- && ix86_lea_for_add_ok (insn, operands)"
- [(set (match_dup 0)
- (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))])
-
(define_insn "*add<mode>_2"
[(set (reg FLAGS_REG)
(compare
commit e7df01bfa9c613749a0d0eb99da245a394ce1573
Author: H.J. Lu <hjl.to...@gmail.com>
Date: Sun Jul 17 16:18:58 2011 -0700
Revert x32 change in ix86_fixup_binary_operands.
diff --git a/gcc/ChangeLog.addr32 b/gcc/ChangeLog.addr32
index fcfaf25..eb0c20b 100644
--- a/gcc/ChangeLog.addr32
+++ b/gcc/ChangeLog.addr32
@@ -1,5 +1,10 @@
2011-07-17 H.J. Lu <hongjiu...@intel.com>
+ * config/i386/i386.c (ix86_fixup_binary_operands): Revert x32
+ change.
+
+2011-07-17 H.J. Lu <hongjiu...@intel.com>
+
* config/i386/i386.md (*lea_0_x32): Removed.
(*lea_2_x32): Likewise.
(*lea_2_zext_x32): Likewise.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index c8989ed..d4b7c2e 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -15646,16 +15646,6 @@ ix86_fixup_binary_operands (enum rtx_code code, enum
machine_mode mode,
else
src2 = force_reg (mode, src2);
}
- else
- {
- /* Support 32bit address in x32 mode. */
- if (TARGET_X32
- && code == PLUS
- && !MEM_P (dst)
- && !MEM_P (src1)
- && MEM_P (src2) )
- src2 = force_reg (mode, src2);
- }
/* If the destination is memory, and we do not have matching source
operands, do things in registers. */
commit f448ba8b4ca9addfd3e699f6d42faa6c82a82d08
Author: H.J. Lu <hjl.to...@gmail.com>
Date: Sun Jul 17 17:15:32 2011 -0700
Don't support 32bit address in x32 mode in ix86_decompose_address.
diff --git a/gcc/ChangeLog.addr32 b/gcc/ChangeLog.addr32
index eb0c20b..506d843 100644
--- a/gcc/ChangeLog.addr32
+++ b/gcc/ChangeLog.addr32
@@ -1,5 +1,10 @@
2011-07-17 H.J. Lu <hongjiu...@intel.com>
+ * config/i386/i386.c (ix86_decompose_address): Don't support
+ 32bit address in x32 mode.
+
+2011-07-17 H.J. Lu <hongjiu...@intel.com>
+
* config/i386/i386.c (ix86_fixup_binary_operands): Revert x32
change.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d4b7c2e..3359154 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -11116,13 +11116,6 @@ ix86_decompose_address (rtx addr, struct ix86_address
*out)
int retval = 1;
enum ix86_address_seg seg = SEG_DEFAULT;
- /* Support 32bit address in x32 mode. */
- if (TARGET_X32
- && GET_CODE (addr) == ZERO_EXTEND
- && GET_MODE (addr) == Pmode
- && GET_CODE (XEXP (addr, 0)) == PLUS)
- addr = XEXP (addr, 0);
-
if (REG_P (addr) || GET_CODE (addr) == SUBREG)
base = addr;
else if (GET_CODE (addr) == PLUS)
