Ping (https://gcc.gnu.org/ml/gcc-patches/2015-01/msg01436.html).
These are required for float16 patches posted at
https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01332.html
Bootstrapped + check-gcc on arm-none-linux-gnueabihf.
Alan Lawrence wrote:
This parallels the present form of __builtin_aarch64_im_lane_boundsi, and allows
to check lane indices for intrinsics that can otherwise be written in terms of
GCC vector extensions.
The new builtin is not used in this patch but is used in my series of float16_t
intrinsics (https://gcc.gnu.org/ml/gcc-patches/2015-01/msg01434.html), and at
some point in the future we should rewrite existing intrinsics (for other types)
to this form too, but I'm leaving that for a later patch series :).
Cross-tested check-gcc on arm-none-eabi
Bootstrapped on arm-none-linux-gnueabihf cortex-a15
gcc/ChangeLog:
* config/arm/arm-builtins.c (enum arm_builtins):
Add ARM_BUILTIN_NEON_BASE and ARM_BUILTIN_NEON_LANE_CHECK.
(ARM_BUILTIN_NEON_BASE): Rename macro to....
(ARM_BUILTIN_NEON_PATTERN_START): ...this.
(arm_init_neon_builtins): Register __builtin_arm_lane_check.
(arm_expand_neon_builtin): Handle ARM_BUILTIN_NEON_LANE_CHECK.
commit 3d5f2b80dc4527b4874bff458bb047946322028f
Author: Alan Lawrence <alan.lawre...@arm.com>
Date: Mon Dec 8 18:36:30 2014 +0000
Add __builtin_arm_lane_check
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 20d2198..3de2be7 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -546,12 +546,16 @@ enum arm_builtins
#undef CRYPTO2
#undef CRYPTO3
+ ARM_BUILTIN_NEON_BASE,
+ ARM_BUILTIN_NEON_LANE_CHECK = ARM_BUILTIN_NEON_BASE,
+
#include "arm_neon_builtins.def"
ARM_BUILTIN_MAX
};
-#define ARM_BUILTIN_NEON_BASE (ARM_BUILTIN_MAX - ARRAY_SIZE (neon_builtin_data))
+#define ARM_BUILTIN_NEON_PATTERN_START \
+ (ARM_BUILTIN_MAX - ARRAY_SIZE (neon_builtin_data))
#undef CF
#undef VAR1
@@ -910,7 +914,7 @@ arm_init_simd_builtin_scalar_types (void)
static void
arm_init_neon_builtins (void)
{
- unsigned int i, fcode = ARM_BUILTIN_NEON_BASE;
+ unsigned int i, fcode = ARM_BUILTIN_NEON_PATTERN_START;
arm_init_simd_builtin_types ();
@@ -920,6 +924,15 @@ arm_init_neon_builtins (void)
system. */
arm_init_simd_builtin_scalar_types ();
+ tree lane_check_fpr = build_function_type_list (void_type_node,
+ intSI_type_node,
+ intSI_type_node,
+ NULL);
+ arm_builtin_decls[ARM_BUILTIN_NEON_LANE_CHECK] =
+ add_builtin_function ("__builtin_arm_lane_check", lane_check_fpr,
+ ARM_BUILTIN_NEON_LANE_CHECK, BUILT_IN_MD,
+ NULL, NULL_TREE);
+
for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++, fcode++)
{
bool print_type_signature_p = false;
@@ -2183,14 +2196,28 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
return target;
}
-/* Expand a Neon builtin. These are "special" because they don't have symbolic
+/* Expand a Neon builtin, i.e. those registered only if TARGET_NEON holds.
+ Most of these are "special" because they don't have symbolic
constants defined per-instruction or per instruction-variant. Instead, the
required info is looked up in the table neon_builtin_data. */
static rtx
arm_expand_neon_builtin (int fcode, tree exp, rtx target)
{
+ if (fcode == ARM_BUILTIN_NEON_LANE_CHECK)
+ {
+ tree nlanes = CALL_EXPR_ARG (exp, 0);
+ gcc_assert (TREE_CODE (nlanes) == INTEGER_CST);
+ rtx lane_idx = expand_normal (CALL_EXPR_ARG (exp, 1));
+ if (CONST_INT_P (lane_idx))
+ neon_lane_bounds (lane_idx, 0, TREE_INT_CST_LOW (nlanes), exp);
+ else
+ error ("%Klane index must be a constant immediate", exp);
+ /* Don't generate any RTL. */
+ return const0_rtx;
+ }
+
neon_builtin_datum *d =
- &neon_builtin_data[fcode - ARM_BUILTIN_NEON_BASE];
+ &neon_builtin_data[fcode - ARM_BUILTIN_NEON_PATTERN_START];
enum insn_code icode = d->code;
builtin_arg args[SIMD_MAX_BUILTIN_ARGS];
int num_args = insn_data[d->code].n_operands;
