That happens in your patch 2/3/4, which use __builtin_aarch64_im_lane_boundsi,
indeed. Hence I think the SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX approach of the
first patch could well be the right way - initially I thought SIMD_ARG... too
heavyweight, but I think I take that back now.
Really I think we should clean up and stop using q-reg intrinsics to handle
d-regs here. I'm working on a few patches (i.e. targetting the v{st,ld}{2,3,4}*
intrinsics) with that aim now, I think I can make some efficiency improvements
in the process, too....
--Alan
Charles Baylis wrote:
On 14 April 2015 at 14:45, Alan Lawrence <alan.lawre...@arm.com> wrote:
Assuming/hoping that this patch is proposed for new stage 1 ;),
IIRC the approach of using __builtin_aarch64_im_lane_boundsi doesn't
work (results in double error messages), and so the patch needs to be
rewritten to avoid it. However, thanks for your comments, I'll reflect
those in the next version of the patch.
Thanks
Charles
