Hello!
Attached patch prevents non-matching input and output memory operands
for various vextract insn patterns. If an optimization pass propagates
non-matching memory operand to the pattern, then RA can't satisfy
matching "0" constraint.
2015-03-26 Uros Bizjak <ubiz...@gmail.com>
PR target/65561
* config/i386/sse.md (avx512dq_vextract<shuffletype>64x2_1_maskm):
Check operand 4 and operand 0 for equality.
(avx512f_vextract<shuffletype>32x4_1_maskm):
Check operand 6 and operand 0 for equality.
(vec_extract_lo_<mode>_maskm): Check operand 2 and operand 0
for equality.
(vec_extract_hi_<mode>_maskm): Ditto.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32} (where
the ICE doesn't trigger), and by Rainer on x86_64-w64-mingw32, where
the patch fixes reported ICE.
Patch was committed to mainline, similar patch will be committed to 4.9 branch.
Uros.
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md (revision 221687)
+++ config/i386/sse.md (working copy)
@@ -6633,7 +6633,8 @@
(match_operand:QI 5 "register_operand" "k")))]
"TARGET_AVX512DQ
&& (INTVAL (operands[2]) % 2 == 0)
- && (INTVAL (operands[2]) == INTVAL (operands[3]) - 1 )"
+ && (INTVAL (operands[2]) == INTVAL (operands[3]) - 1)
+ && rtx_equal_p (operands[4], operands[0])"
{
operands[2] = GEN_INT ((INTVAL (operands[2])) >> 1);
return "vextract<shuffletype>64x2\t{%2, %1, %0%{%5%}|%0%{%5%}, %1, %2}";
@@ -6660,7 +6661,8 @@
&& ((INTVAL (operands[2]) % 4 == 0)
&& INTVAL (operands[2]) == (INTVAL (operands[3]) - 1)
&& INTVAL (operands[3]) == (INTVAL (operands[4]) - 1)
- && INTVAL (operands[4]) == (INTVAL (operands[5]) - 1))"
+ && INTVAL (operands[4]) == (INTVAL (operands[5]) - 1))
+ && rtx_equal_p (operands[6], operands[0])"
{
operands[2] = GEN_INT ((INTVAL (operands[2])) >> 2);
return "vextract<shuffletype>32x4\t{%2, %1, %0%{%7%}|%0%{%7%}, %1, %2}";
@@ -6777,7 +6779,8 @@
(const_int 2) (const_int 3)]))
(match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
(match_operand:QI 3 "register_operand" "Yk")))]
- "TARGET_AVX512F"
+ "TARGET_AVX512F
+ && rtx_equal_p (operands[2], operands[0])"
"vextract<shuffletype>64x4\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
@@ -6813,7 +6816,8 @@
(const_int 6) (const_int 7)]))
(match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
(match_operand:QI 3 "register_operand" "Yk")))]
- "TARGET_AVX512F"
+ "TARGET_AVX512F
+ && rtx_equal_p (operands[2], operands[0])"
"vextract<shuffletype>64x4\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}"
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
@@ -6847,7 +6851,8 @@
(const_int 14) (const_int 15)]))
(match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
(match_operand:QI 3 "register_operand" "k")))]
- "TARGET_AVX512DQ"
+ "TARGET_AVX512DQ
+ && rtx_equal_p (operands[2], operands[0])"
"vextract<shuffletype>32x8\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
@@ -7071,7 +7076,8 @@
(const_int 2) (const_int 3)]))
(match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
(match_operand:QI 3 "register_operand" "k")))]
- "TARGET_AVX512VL && TARGET_AVX512F"
+ "TARGET_AVX512VL && TARGET_AVX512F
+ && rtx_equal_p (operands[2], operands[0])"
"vextract<shuffletype>32x4\t{$0x0, %1, %0%{3%}|%0%{%3%}, %1, 0x0}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
@@ -7088,10 +7094,9 @@
(const_int 6) (const_int 7)]))
(match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
(match_operand:<ssehalfvecmode> 3 "register_operand" "k")))]
- "TARGET_AVX512F && TARGET_AVX512VL"
-{
- return "vextract<shuffletype>32x4\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}";
-}
+ "TARGET_AVX512F && TARGET_AVX512VL
+ && rtx_equal_p (operands[2], operands[0])"
+ "vextract<shuffletype>32x4\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
