Hi, on ARM we have a code quality regression, because of the strict volatile bitfields handing. The reason is that the current implementation directly jumps to store_fixed_bit_field_1 which emits a sequence of and/or/shift expressions. This turns out to be too complex for combine to figure out the possibility to use a "bfi" instruction.
But if -fno-strict-volatile-bitfields is used store_bit_field can use the
EP_insv code pattern, which results in "bfi" instructions.
The only problem is that that store_bit_field is free to use _any_ possible
access mode. But if we load the value first in a register, we can safely
use store_bit_field on the register and move the result back.
Boot-Strapped and regression-tested on Cortex-M3.
OK for trunk?
Thanks
Bernd.
gcc:
2015-03-05 Bernd Edlinger <bernd.edlin...@hotmail.de>
PR rtl-optimization/65067
* expmed.c (store_bit_field, extract_bit_field): Reworked the
strict volatile bitfield handling.
testsuite:
2015-03-05 Bernd Edlinger <bernd.edlin...@hotmail.de>
* gcc.target/arm/pr65067.c: New test.
patch-volatile-bitfields-2.diff
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