Hi,
I was just flicking through the AArch64 back end and spotted the
little-used "emit_set_insn" function.
I was going to remove it, as it had only one user, but actually it
is an inoffensive little abstraction, so I've applied it throughout
aarch64.c
Bootstrapped on aarch64-none-linux-gnu.
Marcus, Richard, do you want this churn now or in Stage 1?
Cheers,
James
---
2015-02-17 James Greenhalgh <james.greenha...@arm.com>
* config/aarch64/aarch64.c (aarch64_internal_mov_immediate): Use
emit_set_insn to emit simple sets.
(aarch64_expand_mov_immediate): Likewise.
(aarch64_expand_compare_and_swap): Likewise.
(aarch64_split_compare_and_swap): Likewise.
(aarch64_split_atomic_op): Likewise.
(aarch64_gen_adjusted_ldpstp): Likewise.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 39921a7..1b0dce3 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1157,7 +1157,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
if (CONST_INT_P (imm) && aarch64_move_imm (INTVAL (imm), mode))
{
if (generate)
- emit_insn (gen_rtx_SET (VOIDmode, dest, imm));
+ emit_set_insn (dest, imm);
num_insns++;
return num_insns;
}
@@ -1169,8 +1169,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
us anything. */
if (generate)
{
- emit_insn (gen_rtx_SET (VOIDmode, dest,
- GEN_INT (INTVAL (imm) & 0xffff)));
+ emit_set_insn (dest, GEN_INT (INTVAL (imm) & 0xffff));
emit_insn (gen_insv_immsi (dest, GEN_INT (16),
GEN_INT ((INTVAL (imm) >> 16) & 0xffff)));
}
@@ -1207,7 +1206,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
mask = 0xffffll << first_not_ffff_match;
if (generate)
{
- emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val | mask)));
+ emit_set_insn (dest, GEN_INT (val | mask));
emit_insn (gen_insv_immdi (dest, GEN_INT (first_not_ffff_match),
GEN_INT ((val >> first_not_ffff_match)
& 0xffff)));
@@ -1229,8 +1228,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
- emit_insn (gen_rtx_SET (VOIDmode, subtarget,
- GEN_INT (val & mask)));
+ emit_set_insn (subtarget, GEN_INT (val & mask));
emit_insn (gen_adddi3 (dest, subtarget,
GEN_INT (val - (val & mask))));
}
@@ -1242,8 +1240,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
- emit_insn (gen_rtx_SET (VOIDmode, subtarget,
- GEN_INT ((val + comp) & mask)));
+ emit_set_insn (subtarget, GEN_INT ((val + comp) & mask));
emit_insn (gen_adddi3 (dest, subtarget,
GEN_INT (val - ((val + comp) & mask))));
}
@@ -1255,8 +1252,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
- emit_insn (gen_rtx_SET (VOIDmode, subtarget,
- GEN_INT ((val - comp) | ~mask)));
+ emit_set_insn (subtarget, GEN_INT ((val - comp) | ~mask));
emit_insn (gen_adddi3 (dest, subtarget,
GEN_INT (val - ((val - comp) | ~mask))));
}
@@ -1268,8 +1264,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
- emit_insn (gen_rtx_SET (VOIDmode, subtarget,
- GEN_INT (val | ~mask)));
+ emit_set_insn (subtarget, GEN_INT (val | ~mask));
emit_insn (gen_adddi3 (dest, subtarget,
GEN_INT (val - (val | ~mask))));
}
@@ -1291,8 +1286,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
- emit_insn (gen_rtx_SET (VOIDmode, subtarget,
- GEN_INT (aarch64_bitmasks[i])));
+ emit_set_insn (subtarget, GEN_INT (aarch64_bitmasks[i]));
emit_insn (gen_adddi3 (dest, subtarget,
GEN_INT (val - aarch64_bitmasks[i])));
}
@@ -1306,8 +1300,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
{
if (generate)
{
- emit_insn (gen_rtx_SET (VOIDmode, dest,
- GEN_INT (aarch64_bitmasks[i])));
+ emit_set_insn (dest, GEN_INT (aarch64_bitmasks[i]));
emit_insn (gen_insv_immdi (dest, GEN_INT (j),
GEN_INT ((val >> j) & 0xffff)));
}
@@ -1330,8 +1323,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (mode) : dest;
- emit_insn (gen_rtx_SET (VOIDmode, subtarget,
- GEN_INT (aarch64_bitmasks[i])));
+ emit_set_insn (subtarget, GEN_INT (aarch64_bitmasks[i]));
emit_insn (gen_iordi3 (dest, subtarget,
GEN_INT (aarch64_bitmasks[j])));
}
@@ -1349,8 +1341,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
if (generate)
{
subtarget = subtargets ? gen_reg_rtx (mode) : dest;
- emit_insn (gen_rtx_SET (VOIDmode, subtarget,
- GEN_INT (aarch64_bitmasks[j])));
+ emit_set_insn (subtarget, GEN_INT (aarch64_bitmasks[j]));
emit_insn (gen_anddi3 (dest, subtarget,
GEN_INT (aarch64_bitmasks[i])));
}
@@ -1365,8 +1356,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
/* Set either first three quarters or all but the third. */
mask = 0xffffll << (16 - first_not_ffff_match);
if (generate)
- emit_insn (gen_rtx_SET (VOIDmode, dest,
- GEN_INT (val | mask | 0xffffffff00000000ull)));
+ emit_set_insn (dest, GEN_INT (val | mask | 0xffffffff00000000ull));
num_insns ++;
/* Now insert other two quarters. */
@@ -1394,8 +1384,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
if (first)
{
if (generate)
- emit_insn (gen_rtx_SET (VOIDmode, dest,
- GEN_INT (val & mask)));
+ emit_set_insn (dest, GEN_INT (val & mask));
num_insns ++;
first = false;
}
@@ -1449,7 +1438,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
gcc_assert (mem);
if (mode != ptr_mode)
mem = gen_rtx_ZERO_EXTEND (mode, mem);
- emit_insn (gen_rtx_SET (VOIDmode, dest, mem));
+ emit_set_insn (dest, mem);
return;
case SYMBOL_SMALL_TLSGD:
@@ -1481,12 +1470,12 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
if (!CONST_INT_P (imm))
{
if (GET_CODE (imm) == HIGH)
- emit_insn (gen_rtx_SET (VOIDmode, dest, imm));
+ emit_set_insn (dest, imm);
else
{
rtx mem = force_const_mem (mode, imm);
gcc_assert (mem);
- emit_insn (gen_rtx_SET (VOIDmode, dest, mem));
+ emit_set_insn (dest, mem);
}
return;
@@ -9059,7 +9048,7 @@ aarch64_expand_compare_and_swap (rtx operands[])
x = gen_rtx_REG (CCmode, CC_REGNUM);
x = gen_rtx_EQ (SImode, x, const0_rtx);
- emit_insn (gen_rtx_SET (VOIDmode, bval, x));
+ emit_set_insn (bval, x);
}
/* Split a compare and swap pattern. */
@@ -9110,7 +9099,7 @@ aarch64_split_compare_and_swap (rtx operands[])
{
cond = gen_rtx_REG (CCmode, CC_REGNUM);
x = gen_rtx_COMPARE (CCmode, scratch, const0_rtx);
- emit_insn (gen_rtx_SET (VOIDmode, cond, x));
+ emit_set_insn (cond, x);
}
emit_label (label2);
@@ -9148,9 +9137,9 @@ aarch64_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
case NOT:
x = gen_rtx_AND (wmode, old_out, value);
- emit_insn (gen_rtx_SET (VOIDmode, new_out, x));
+ emit_set_insn (new_out, x);
x = gen_rtx_NOT (wmode, new_out);
- emit_insn (gen_rtx_SET (VOIDmode, new_out, x));
+ emit_set_insn (new_out, x);
break;
case MINUS:
@@ -9163,7 +9152,7 @@ aarch64_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
default:
x = gen_rtx_fmt_ee (code, wmode, old_out, value);
- emit_insn (gen_rtx_SET (VOIDmode, new_out, x));
+ emit_set_insn (new_out, x);
break;
}
@@ -11168,8 +11157,7 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load,
}
/* Emit adjusting instruction. */
- emit_insn (gen_rtx_SET (VOIDmode, operands[8],
- plus_constant (DImode, base, adj_off)));
+ emit_set_insn (operands[8], plus_constant (DImode, base, adj_off));
/* Emit ldp/stp instructions. */
t1 = gen_rtx_SET (VOIDmode, operands[0], operands[1]);
t2 = gen_rtx_SET (VOIDmode, operands[2], operands[3]);
