On Fri, Feb 6, 2015 at 9:41 AM, Michael Meissner <meiss...@linux.vnet.ibm.com> wrote: > This patch fixes PR target/64205, which was caused due to my previous patch to > add the -mupper-regs support for scalar floating point to occupy the VSX > floating point registers that are overlaid on top of the traditional Altivec > registers, starting with ISA 2.06 (power7). > > The problem was, I added secondary reload handlers for SDmode unconditionally. > On systems before ISA 2.06, there are no stores and loads for 32-bit SDmode in > a floating point register, and so you can't do normal secondary reload > operations on this (you have to do a 64-bit store and a 32-bit load on the > bottom bits). > > I have tested this with a full bootstrap on PowerPC 64-bit systems with no > regressions. In addition, I built a bootstrap compiler using the > --with-cpu=G5 > option and it succeeded. Is it ok to install the patches in trunk, and in any > branches that the upper regs patches were applied to? > > [gcc] > 2015-02-06 Michael Meissner <meiss...@linux.vnet.ibm.com> > > PR target/64205 > * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Do not > add a general secondary reload handler for SDmode, unless we have > both read/write support for SDmode. > > [gcc/testsuite] > 2015-02-06 Michael Meissner <meiss...@linux.vnet.ibm.com> > > PR target/64205 > * gcc.target/powerpc/pr64205.c: New file.
Please clarify the comments in rs6000.c. Too many double negatives and ambiguous terms. For example, "Use SDmode reload patterns if float load/store integer word instructions are available." Okay with an improved comment. Thanks, David
