On Wed, Jan 28, 2015 at 12:32:45PM +0000, Alan Lawrence wrote: > Ok for stage 4?
This is a regression from 4.9, so once we iron out some nits, it should be. > gcc/ChangeLog: > > * config/aarch64/aarch64.md (*xor_one_cmpl<mode>3): Use FP_REGNUM_P > as split condition. And a testcase, please! > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index > bc49fbe68a978b3ca069c6d084f542773df84bcb..d4b3f7b03ba0ab570cec5ce862e8c5f38f417ed1 > 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -3054,7 +3054,7 @@ > (match_operand:GPI 2 "register_operand" "r,w"))))] > "" > "eon\\t%<w>0, %<w>1, %<w>2" ;; For GPR registers (only). This should be: "@ eon\\t%<w>0, %<w>1, %<w>2 #" which would have forced a split. Your patch is useful regardless, as I guess we could have ended up needlessly splitting if we got unlucky with whatever had been left in which_alternative. Thanks, James > - "reload_completed && (which_alternative == 1)" ;; For SIMD registers. > + "reload_completed && FP_REGNUM_P (REGNO (operands[0]))" ;; For SIMD > registers. > [(set (match_operand:GPI 0 "register_operand" "=w") > (xor:GPI (match_operand:GPI 1 "register_operand" "w") > (match_operand:GPI 2 "register_operand" "w")))
