On 16 January 2015 at 19:15, Tejas Belagod <tejas.bela...@arm.com> wrote:
> On 13/01/15 15:18, Christophe Lyon wrote:
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vmovl.c: New file.
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
>> new file mode 100644
>> index 0000000..427c9ba
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
>> @@ -0,0 +1,77 @@
>> +#include <arm_neon.h>
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected results. */
>> +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333
>> };
>> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
>> +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
>> + 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
>> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
>> + 0xfffffff2, 0xfffffff3 };
>> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
>> + 0xfffffffffffffff1 };
>> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
>> + 0xf4, 0xf5, 0xf6, 0xf7 };
>> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3
>> };
>> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffff0, 0xfffffff1 };
>> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33,
>> + 0x33, 0x33, 0x33, 0x33 };
>> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
>> + 0x3333, 0x3333, 0x3333, 0x3333 };
>> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
>> + 0x33333333, 0x33333333 };
>> +
>
>
> No poly or float for vmovl.
>
Here is a new version, with more cleanup: only 16x8, 32x4 and 64x2
variants are necessary.
> Otherwise, LGTM.
>
> Tejas.
>
>
From 2f56acd54cee2d9b9b62de9e624fb2a64f114101 Mon Sep 17 00:00:00 2001
From: Christophe Lyon <christophe.l...@linaro.org>
Date: Wed, 10 Dec 2014 17:24:48 +0100
Subject: [[ARM/AArch64][testsuite] 21/36] Add vmovl tests.
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
new file mode 100644
index 0000000..fd94d72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c
@@ -0,0 +1,52 @@
+#include <arm_neon.h>
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results. */
+VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3,
+ 0xfff4, 0xfff5, 0xfff6, 0xfff7 };
+VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1,
+ 0xfffffff2, 0xfffffff3 };
+VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0,
+ 0xfffffffffffffff1 };
+VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3,
+ 0xf4, 0xf5, 0xf6, 0xf7 };
+VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 };
+VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffff0, 0xfffffff1 };
+
+#define TEST_MSG "VMOVL"
+void exec_vmovl (void)
+{
+ /* Basic test: vec128=vmovl(vec64), then store the result. */
+#define TEST_VMOVL(T1, T2, W, W2, N) \
+ VECT_VAR(vector128, T1, W2, N) = \
+ vmovl_##T2##W(VECT_VAR(vector64, T1, W, N)); \
+ vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector128, T1, W2, N))
+
+ DECL_VARIABLE_64BITS_VARIANTS(vector64);
+ DECL_VARIABLE_128BITS_VARIANTS(vector128);
+
+ TEST_MACRO_64BITS_VARIANTS_2_5(VLOAD, vector64, buffer);
+
+ clean_results ();
+
+ TEST_VMOVL(int, s, 8, 16, 8);
+ TEST_VMOVL(int, s, 16, 32, 4);
+ TEST_VMOVL(int, s, 32, 64, 2);
+ TEST_VMOVL(uint, u, 8, 16, 8);
+ TEST_VMOVL(uint, u, 16, 32, 4);
+ TEST_VMOVL(uint, u, 32, 64, 2);
+
+ CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, "");
+ CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
+ CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
+ CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, "");
+}
+
+int main (void)
+{
+ exec_vmovl ();
+ return 0;
+}
--
2.1.0
