Hi,
This change:
+2014-12-05 Martin Jambor mjam...@suse.cz
+
PR ipa/64192
ipa-prop.c (ipa_compute_jump_functions_for_edge): Convert alignment
from bits to bytes after checking they are byte-aligned.
+
causes this regression on AArch64.
FAIL: gcc.target/aarch64/vect-movi.c scan-assembler movi\\tv[0-9]+.4s,
0xab, msl 16
FAIL: gcc.target/aarch64/vect-movi.c scan-assembler movi\\tv[0-9]+.4s,
0xab, msl 8
FAIL: gcc.target/aarch64/vect-movi.c scan-assembler mvni\\tv[0-9]+.4s,
0xab, msl 16
FAIL: gcc.target/aarch64/vect-movi.c scan-assembler mvni\\tv[0-9]+.4s,
0xab, msl 8
It causes AArch64 vector cost model to vectorize the loops in the test
case with a VF = 2 on A53/default and VF = 4 for A57.
A53/default:
movi v0.2s, 0xab, msl 8
str d0, [x0]
str d0, [x0, 8]
str d0, [x0, 16]
str d0, [x0, 24]
str d0, [x0, 32]
str d0, [x0, 40]
str d0, [x0, 48]
str d0, [x0, 56]
vs. A57
movi v0.4s, 0xab, msl 8
str q0, [x0]
str q0, [x0, 16]
str q0, [x0, 32]
str q0, [x0, 48]
But the test case isn't checking for a per-core optimized code, just
whether we vectorize for MOVI or not. So, this patch improves reg exp to
make sure the compiler vectorizes the code for either vectorization factor.
OK for trunk?
Thanks,
Tejas.
Changelog:
gcc/testsuite:
* gcc.target/aarch64/vect-movi.c: Check for vectorization for
64-bit and 128-bit.diff --git a/gcc/testsuite/gcc.target/aarch64/vect-movi.c
b/gcc/testsuite/gcc.target/aarch64/vect-movi.c
index 59a0bd5..d28a71d 100644
--- a/gcc/testsuite/gcc.target/aarch64/vect-movi.c
+++ b/gcc/testsuite/gcc.target/aarch64/vect-movi.c
@@ -10,7 +10,7 @@ movi_msl8 (int *__restrict a)
{
int i;
- /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */
+ /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.\[42\]s, 0xab, msl 8" } }
*/
for (i = 0; i < N; i++)
a[i] = 0xabff;
}
@@ -20,7 +20,7 @@ movi_msl16 (int *__restrict a)
{
int i;
- /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */
+ /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.\[42\]s, 0xab, msl 16" } }
*/
for (i = 0; i < N; i++)
a[i] = 0xabffff;
}
@@ -30,7 +30,7 @@ mvni_msl8 (int *__restrict a)
{
int i;
- /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */
+ /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.\[42\]s, 0xab, msl 8" } }
*/
for (i = 0; i < N; i++)
a[i] = 0xffff5400;
}
@@ -40,7 +40,7 @@ mvni_msl16 (int *__restrict a)
{
int i;
- /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */
+ /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.\[42\]s, 0xab, msl 16" } }
*/
for (i = 0; i < N; i++)
a[i] = 0xff540000;
}
