On Mon, Jul 4, 2011 at 3:18 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
> On Mon, Jul 4, 2011 at 7:13 AM, H.J. Lu <hjl.to...@gmail.com> wrote:
>
>>>>> In one SSE2 int->float split, when TARGET_USE_VECTOR_CONVERTS is true,
>>>>> TARGET_INTER_UNIT_MOVES is false and GENERAL_REG_P (op1) is true. we
>>>>> will get gcc_unreachable. This patch removes TARGET_INTER_UNIT_MOVES
>>>>> check. OK for trunk?
>>>>
>>>> This will result in register allocation failure. Operand 0 of
>>
>> That particular sse2_loadld insn matches:
>>
>> (insn 49 22 50 5 (set (reg:V4SI 21 xmm0 [83])
>> (vec_merge:V4SI (vec_duplicate:V4SI (reg/v:SI 1 dx [orig:64
>> test ] [64]))
>> (const_vector:V4SI [
>> (const_int 0 [0])
>> (const_int 0 [0])
>> (const_int 0 [0])
>> (const_int 0 [0])
>> ])
>> (const_int 1 [0x1]))) x.i:11 1365 {vec_setv4si_0}
>> (nil))
>>
>
> Yes, but it should not be generated for !TARGET_INTER_UNIT_MOVES. The
> constraint should be Yi, but then we don't shadow other alternatives
> correctly.
>
>>>> sse2_loadld pattern has conditional constraint Yi that depends on
>>>> TARGET_INTER_UNIT_MOVES, so we can't blindly generate sse2_loadld
>>>> after reload. I'm testing attached patch.
>>>>
>>>> BTW: Do you perhaps have a testcase for this problem?
>>>
>>> I have a testcase. But it needs a new x86 optimization we are working on it.
>>>
>>>> 2011-07-03 Uros Bizjak <ubiz...@gmail.com>
>>>>
>>>> PR target/49600
>>>> * config/i386/i386.md (SSE2 int->float split): Push operand 1 in
>>>> general register to memory for !TARGET_INTER_UNIT_MOVES.
>>>>
>>>
>>> I will give it a try.
>>>
>>
>> It doesn't work: I still got
>
> Yes, I later noticed that I have changed the wrong pattern (the one
> with memory clobber) ;( . Attached is the correct patch.
>
This works. Can you check it in?
Thanks.
--
H.J.
