On 25/06/11 15:12, Bernd Schmidt wrote:
That all sounds good, but missing from this list is something that
occurs on many CPUs - widening from the high part of a register. The
current machinery only recognizes lowxlow widening multiplication, but
hardware often exists for highxlow and highxhigh. For example, Blackfin
has "<su_optab>hisi_lh"/hl/hh instruction patterns; C6X also has a full
set; ARM has mulhisi3tb/bt/tt.
Do you think it will be possible to extend your new framework to handle
this case as well?
No, I can't think of a way to implement widening from the high part
using anything like my framework.
I mean, what I've done is add a new dimension to the optab table, but
not changed the meaning of that optab. The expand pass has to look at
the input types to know what insn to use, but it doesn't need to look
any further than that. If I added yet another dimension to cover expand
from high part, then we could detect that in convert_mult_to_widen (and
maybe clean it up), but the expander would still have to re-detect it
later on.
I would think that the best way to implement that would still be to add
a new optab entry, new tree code, etc., etc., and then fix up all the
"if (optab == smul_widen_optab)" and such that would need to consider it.
In any case, on ARM at any rate, the combine pass already combines shift
and widening-mult patterns quite reliably (I committed at a patch for
that not so long ago).
Andrew
