On Mon, Jun 6, 2011 at 3:04 PM, Richard Sandiford <richard.sandif...@linaro.org> wrote: > Richard Guenther <richard.guent...@gmail.com> writes: >> Thanks. I would hope that we eventually can get rid of the >> pattern recognizer ... at least for SSE there is also always >> a scalar variant instruction for each vectorized one. > > AFAIK, that isn't true for ARM and NEON. E.g. I don't know of a single > instruction that does the scalar equivalent of things like VADDHN > (add values and narrow to high half), VSUBL.U32 (subtract two values > and extend the result), etc. > > FWIW, I think MIPS only has minimum and maximum operations for paired > floats, not for single floats or doubles. I don't have the manuals to > hand to check though. > > It's probably OK for the particular case of widening multiplications. > It sounded like you were making a more general statement though. > If so, I think we should try to avoid assuming that every vectorisable > operation has an equivalent scalar machine instruction.
Hmm, too bad ;) Yes, I was suggesting that we assume that. I guess for now we can go with the vectorizer pattern matching enhancement and re-visit re-ordering the passes later (I don't have time right now to look into the reported issue). Thanks, Richard. > Richard >
