On Tue, 10 May 2011, Bernd Schmidt wrote: > On C6X, every jump instruction has 5 delay slots which can be filled > with normally scheduled instructions. With an issue width of 8 > insns/cycle, this means that up to 40 insns can be issued after the jump > insn before the jump's side-effect takes place. I didn't particularaly > feel like using reorg.c to deal with this,
No kidding... multi-delay-slot bugs just waiting for you... > hence these scheduler patches. THANK YOU for these first steps! brgds, H-P
